411 lines
11 KiB
C
411 lines
11 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __ALPHA_TITAN__H__
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#define __ALPHA_TITAN__H__
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#include <linux/types.h>
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#include <asm/compiler.h>
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/*
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* TITAN is the internal names for a core logic chipset which provides
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* memory controller and PCI/AGP access for 21264 based systems.
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*
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* This file is based on:
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*
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* Titan Chipset Engineering Specification
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* Revision 0.12
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* 13 July 1999
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*
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*/
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/* XXX: Do we need to conditionalize on this? */
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#ifdef USE_48_BIT_KSEG
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#define TI_BIAS 0x80000000000UL
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#else
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#define TI_BIAS 0x10000000000UL
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#endif
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/*
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* CChip, DChip, and PChip registers
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*/
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typedef struct {
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volatile unsigned long csr __attribute__((aligned(64)));
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} titan_64;
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typedef struct {
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titan_64 csc;
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titan_64 mtr;
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titan_64 misc;
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titan_64 mpd;
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titan_64 aar0;
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titan_64 aar1;
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titan_64 aar2;
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titan_64 aar3;
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titan_64 dim0;
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titan_64 dim1;
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titan_64 dir0;
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titan_64 dir1;
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titan_64 drir;
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titan_64 prben;
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titan_64 iic0;
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titan_64 iic1;
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titan_64 mpr0;
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titan_64 mpr1;
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titan_64 mpr2;
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titan_64 mpr3;
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titan_64 rsvd[2];
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titan_64 ttr;
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titan_64 tdr;
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titan_64 dim2;
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titan_64 dim3;
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titan_64 dir2;
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titan_64 dir3;
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titan_64 iic2;
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titan_64 iic3;
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titan_64 pwr;
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titan_64 reserved[17];
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titan_64 cmonctla;
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titan_64 cmonctlb;
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titan_64 cmoncnt01;
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titan_64 cmoncnt23;
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titan_64 cpen;
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} titan_cchip;
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typedef struct {
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titan_64 dsc;
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titan_64 str;
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titan_64 drev;
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titan_64 dsc2;
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} titan_dchip;
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typedef struct {
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titan_64 wsba[4];
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titan_64 wsm[4];
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titan_64 tba[4];
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titan_64 pctl;
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titan_64 plat;
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titan_64 reserved0[2];
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union {
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struct {
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titan_64 serror;
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titan_64 serren;
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titan_64 serrset;
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titan_64 reserved0;
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titan_64 gperror;
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titan_64 gperren;
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titan_64 gperrset;
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titan_64 reserved1;
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titan_64 gtlbiv;
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titan_64 gtlbia;
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titan_64 reserved2[2];
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titan_64 sctl;
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titan_64 reserved3[3];
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} g;
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struct {
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titan_64 agperror;
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titan_64 agperren;
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titan_64 agperrset;
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titan_64 agplastwr;
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titan_64 aperror;
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titan_64 aperren;
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titan_64 aperrset;
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titan_64 reserved0;
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titan_64 atlbiv;
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titan_64 atlbia;
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titan_64 reserved1[6];
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} a;
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} port_specific;
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titan_64 sprst;
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titan_64 reserved1[31];
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} titan_pachip_port;
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typedef struct {
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titan_pachip_port g_port;
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titan_pachip_port a_port;
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} titan_pachip;
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#define TITAN_cchip ((titan_cchip *)(IDENT_ADDR+TI_BIAS+0x1A0000000UL))
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#define TITAN_dchip ((titan_dchip *)(IDENT_ADDR+TI_BIAS+0x1B0000800UL))
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#define TITAN_pachip0 ((titan_pachip *)(IDENT_ADDR+TI_BIAS+0x180000000UL))
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#define TITAN_pachip1 ((titan_pachip *)(IDENT_ADDR+TI_BIAS+0x380000000UL))
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extern unsigned TITAN_agp;
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extern int TITAN_bootcpu;
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/*
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* TITAN PA-chip Window Space Base Address register.
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* (WSBA[0-2])
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*/
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#define wsba_m_ena 0x1
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#define wsba_m_sg 0x2
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#define wsba_m_addr 0xFFF00000
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#define wmask_k_sz1gb 0x3FF00000
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union TPAchipWSBA {
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struct {
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unsigned wsba_v_ena : 1;
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unsigned wsba_v_sg : 1;
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unsigned wsba_v_rsvd1 : 18;
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unsigned wsba_v_addr : 12;
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unsigned wsba_v_rsvd2 : 32;
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} wsba_r_bits;
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int wsba_q_whole [2];
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};
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/*
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* TITAN PA-chip Control Register
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* This definition covers both the G-Port GPCTL and the A-PORT APCTL.
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* Bits <51:0> are the same in both cases. APCTL<63:52> are only
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* applicable to AGP.
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*/
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#define pctl_m_fbtb 0x00000001
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#define pctl_m_thdis 0x00000002
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#define pctl_m_chaindis 0x00000004
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#define pctl_m_tgtlat 0x00000018
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#define pctl_m_hole 0x00000020
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#define pctl_m_mwin 0x00000040
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#define pctl_m_arbena 0x00000080
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#define pctl_m_prigrp 0x0000FF00
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#define pctl_m_ppri 0x00010000
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#define pctl_m_pcispd66 0x00020000
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#define pctl_m_cngstlt 0x003C0000
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#define pctl_m_ptpdesten 0x3FC00000
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#define pctl_m_dpcen 0x40000000
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#define pctl_m_apcen 0x0000000080000000UL
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#define pctl_m_dcrtv 0x0000000300000000UL
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#define pctl_m_en_stepping 0x0000000400000000UL
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#define apctl_m_rsvd1 0x000FFFF800000000UL
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#define apctl_m_agp_rate 0x0030000000000000UL
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#define apctl_m_agp_sba_en 0x0040000000000000UL
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#define apctl_m_agp_en 0x0080000000000000UL
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#define apctl_m_rsvd2 0x0100000000000000UL
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#define apctl_m_agp_present 0x0200000000000000UL
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#define apctl_agp_hp_rd 0x1C00000000000000UL
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#define apctl_agp_lp_rd 0xE000000000000000UL
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#define gpctl_m_rsvd 0xFFFFFFF800000000UL
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union TPAchipPCTL {
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struct {
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unsigned pctl_v_fbtb : 1; /* A/G [0] */
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unsigned pctl_v_thdis : 1; /* A/G [1] */
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unsigned pctl_v_chaindis : 1; /* A/G [2] */
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unsigned pctl_v_tgtlat : 2; /* A/G [4:3] */
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unsigned pctl_v_hole : 1; /* A/G [5] */
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unsigned pctl_v_mwin : 1; /* A/G [6] */
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unsigned pctl_v_arbena : 1; /* A/G [7] */
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unsigned pctl_v_prigrp : 8; /* A/G [15:8] */
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unsigned pctl_v_ppri : 1; /* A/G [16] */
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unsigned pctl_v_pcispd66 : 1; /* A/G [17] */
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unsigned pctl_v_cngstlt : 4; /* A/G [21:18] */
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unsigned pctl_v_ptpdesten : 8; /* A/G [29:22] */
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unsigned pctl_v_dpcen : 1; /* A/G [30] */
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unsigned pctl_v_apcen : 1; /* A/G [31] */
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unsigned pctl_v_dcrtv : 2; /* A/G [33:32] */
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unsigned pctl_v_en_stepping :1; /* A/G [34] */
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unsigned apctl_v_rsvd1 : 17; /* A [51:35] */
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unsigned apctl_v_agp_rate : 2; /* A [53:52] */
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unsigned apctl_v_agp_sba_en : 1; /* A [54] */
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unsigned apctl_v_agp_en : 1; /* A [55] */
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unsigned apctl_v_rsvd2 : 1; /* A [56] */
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unsigned apctl_v_agp_present : 1; /* A [57] */
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unsigned apctl_v_agp_hp_rd : 3; /* A [60:58] */
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unsigned apctl_v_agp_lp_rd : 3; /* A [63:61] */
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} pctl_r_bits;
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unsigned int pctl_l_whole [2];
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unsigned long pctl_q_whole;
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};
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/*
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* SERROR / SERREN / SERRSET
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*/
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union TPAchipSERR {
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struct {
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unsigned serr_v_lost_uecc : 1; /* [0] */
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unsigned serr_v_uecc : 1; /* [1] */
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unsigned serr_v_cre : 1; /* [2] */
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unsigned serr_v_nxio : 1; /* [3] */
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unsigned serr_v_lost_cre : 1; /* [4] */
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unsigned serr_v_rsvd0 : 10; /* [14:5] */
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unsigned serr_v_addr : 32; /* [46:15] */
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unsigned serr_v_rsvd1 : 5; /* [51:47] */
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unsigned serr_v_source : 2; /* [53:52] */
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unsigned serr_v_cmd : 2; /* [55:54] */
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unsigned serr_v_syn : 8; /* [63:56] */
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} serr_r_bits;
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unsigned int serr_l_whole[2];
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unsigned long serr_q_whole;
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};
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/*
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* GPERROR / APERROR / GPERREN / APERREN / GPERRSET / APERRSET
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*/
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union TPAchipPERR {
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struct {
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unsigned long perr_v_lost : 1; /* [0] */
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unsigned long perr_v_serr : 1; /* [1] */
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unsigned long perr_v_perr : 1; /* [2] */
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unsigned long perr_v_dcrto : 1; /* [3] */
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unsigned long perr_v_sge : 1; /* [4] */
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unsigned long perr_v_ape : 1; /* [5] */
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unsigned long perr_v_ta : 1; /* [6] */
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unsigned long perr_v_dpe : 1; /* [7] */
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unsigned long perr_v_nds : 1; /* [8] */
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unsigned long perr_v_iptpr : 1; /* [9] */
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unsigned long perr_v_iptpw : 1; /* [10] */
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unsigned long perr_v_rsvd0 : 3; /* [13:11] */
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unsigned long perr_v_addr : 33; /* [46:14] */
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unsigned long perr_v_dac : 1; /* [47] */
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unsigned long perr_v_mwin : 1; /* [48] */
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unsigned long perr_v_rsvd1 : 3; /* [51:49] */
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unsigned long perr_v_cmd : 4; /* [55:52] */
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unsigned long perr_v_rsvd2 : 8; /* [63:56] */
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} perr_r_bits;
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unsigned int perr_l_whole[2];
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unsigned long perr_q_whole;
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};
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/*
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* AGPERROR / AGPERREN / AGPERRSET
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*/
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union TPAchipAGPERR {
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struct {
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unsigned agperr_v_lost : 1; /* [0] */
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unsigned agperr_v_lpqfull : 1; /* [1] */
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unsigned apgerr_v_hpqfull : 1; /* [2] */
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unsigned agperr_v_rescmd : 1; /* [3] */
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unsigned agperr_v_ipte : 1; /* [4] */
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unsigned agperr_v_ptp : 1; /* [5] */
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unsigned agperr_v_nowindow : 1; /* [6] */
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unsigned agperr_v_rsvd0 : 8; /* [14:7] */
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unsigned agperr_v_addr : 32; /* [46:15] */
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unsigned agperr_v_rsvd1 : 1; /* [47] */
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unsigned agperr_v_dac : 1; /* [48] */
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unsigned agperr_v_mwin : 1; /* [49] */
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unsigned agperr_v_cmd : 3; /* [52:50] */
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unsigned agperr_v_length : 6; /* [58:53] */
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unsigned agperr_v_fence : 1; /* [59] */
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unsigned agperr_v_rsvd2 : 4; /* [63:60] */
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} agperr_r_bits;
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unsigned int agperr_l_whole[2];
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unsigned long agperr_q_whole;
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};
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/*
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* Memory spaces:
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* Hose numbers are assigned as follows:
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* 0 - pachip 0 / G Port
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* 1 - pachip 1 / G Port
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* 2 - pachip 0 / A Port
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* 3 - pachip 1 / A Port
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*/
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#define TITAN_HOSE_SHIFT (33)
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#define TITAN_HOSE(h) (((unsigned long)(h)) << TITAN_HOSE_SHIFT)
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#define TITAN_BASE (IDENT_ADDR + TI_BIAS)
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#define TITAN_MEM(h) (TITAN_BASE+TITAN_HOSE(h)+0x000000000UL)
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#define _TITAN_IACK_SC(h) (TITAN_BASE+TITAN_HOSE(h)+0x1F8000000UL)
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#define TITAN_IO(h) (TITAN_BASE+TITAN_HOSE(h)+0x1FC000000UL)
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#define TITAN_CONF(h) (TITAN_BASE+TITAN_HOSE(h)+0x1FE000000UL)
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#define TITAN_HOSE_MASK TITAN_HOSE(3)
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#define TITAN_IACK_SC _TITAN_IACK_SC(0) /* hack! */
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/*
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* The canonical non-remaped I/O and MEM addresses have these values
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* subtracted out. This is arranged so that folks manipulating ISA
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* devices can use their familiar numbers and have them map to bus 0.
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*/
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#define TITAN_IO_BIAS TITAN_IO(0)
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#define TITAN_MEM_BIAS TITAN_MEM(0)
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/* The IO address space is larger than 0xffff */
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#define TITAN_IO_SPACE (TITAN_CONF(0) - TITAN_IO(0))
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/* TIG Space */
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#define TITAN_TIG_SPACE (TITAN_BASE + 0x100000000UL)
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/* Offset between ram physical addresses and pci64 DAC bus addresses. */
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/* ??? Just a guess. Ought to confirm it hasn't been moved. */
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#define TITAN_DAC_OFFSET (1UL << 40)
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/*
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* Data structure for handling TITAN machine checks:
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*/
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#define SCB_Q_SYSERR 0x620
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#define SCB_Q_PROCERR 0x630
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#define SCB_Q_SYSMCHK 0x660
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#define SCB_Q_PROCMCHK 0x670
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#define SCB_Q_SYSEVENT 0x680 /* environmental / system management */
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struct el_TITAN_sysdata_mcheck {
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u64 summary; /* 0x00 */
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u64 c_dirx; /* 0x08 */
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u64 c_misc; /* 0x10 */
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u64 p0_serror; /* 0x18 */
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u64 p0_gperror; /* 0x20 */
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u64 p0_aperror; /* 0x28 */
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u64 p0_agperror;/* 0x30 */
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u64 p1_serror; /* 0x38 */
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u64 p1_gperror; /* 0x40 */
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u64 p1_aperror; /* 0x48 */
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u64 p1_agperror;/* 0x50 */
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};
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/*
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* System area for a privateer 680 environmental/system management mcheck
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*/
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struct el_PRIVATEER_envdata_mcheck {
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u64 summary; /* 0x00 */
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u64 c_dirx; /* 0x08 */
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u64 smir; /* 0x10 */
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u64 cpuir; /* 0x18 */
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u64 psir; /* 0x20 */
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u64 fault; /* 0x28 */
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u64 sys_doors; /* 0x30 */
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u64 temp_warn; /* 0x38 */
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u64 fan_ctrl; /* 0x40 */
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u64 code; /* 0x48 */
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u64 reserved; /* 0x50 */
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};
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#ifdef __KERNEL__
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#ifndef __EXTERN_INLINE
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#define __EXTERN_INLINE extern inline
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#define __IO_EXTERN_INLINE
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#endif
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/*
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* I/O functions:
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*
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* TITAN, a 21??? PCI/memory support chipset for the EV6 (21264)
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* can only use linear accesses to get at PCI/AGP memory and I/O spaces.
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*/
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/*
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* Memory functions. all accesses are done through linear space.
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*/
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extern void __iomem *titan_ioportmap(unsigned long addr);
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extern void __iomem *titan_ioremap(unsigned long addr, unsigned long size);
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extern void titan_iounmap(volatile void __iomem *addr);
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__EXTERN_INLINE int titan_is_ioaddr(unsigned long addr)
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{
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return addr >= TITAN_BASE;
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}
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extern int titan_is_mmio(const volatile void __iomem *addr);
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#undef __IO_PREFIX
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#define __IO_PREFIX titan
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#define titan_trivial_rw_bw 1
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#define titan_trivial_rw_lq 1
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#define titan_trivial_io_bw 1
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#define titan_trivial_io_lq 1
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#define titan_trivial_iounmap 0
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#include <asm/io_trivial.h>
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#ifdef __IO_EXTERN_INLINE
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#undef __EXTERN_INLINE
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#undef __IO_EXTERN_INLINE
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#endif
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#endif /* __KERNEL__ */
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#endif /* __ALPHA_TITAN__H__ */
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