802 lines
20 KiB
Plaintext
802 lines
20 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Device Tree Source for AM4372 SoC
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*
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* Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
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*/
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#include <dt-bindings/bus/ti-sysc.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/am4.h>
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/ {
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compatible = "ti,am4372", "ti,am43";
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interrupt-parent = <&wakeupgen>;
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#address-cells = <1>;
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#size-cells = <1>;
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chosen { };
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memory@0 {
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device_type = "memory";
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reg = <0 0>;
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};
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aliases {
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i2c0 = &i2c0;
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i2c1 = &i2c1;
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i2c2 = &i2c2;
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serial0 = &uart0;
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serial1 = &uart1;
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serial2 = &uart2;
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serial3 = &uart3;
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serial4 = &uart4;
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serial5 = &uart5;
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ethernet0 = &cpsw_port1;
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ethernet1 = &cpsw_port2;
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spi0 = &qspi;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu: cpu@0 {
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compatible = "arm,cortex-a9";
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enable-method = "ti,am4372";
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device_type = "cpu";
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reg = <0>;
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clocks = <&dpll_mpu_ck>;
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clock-names = "cpu";
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operating-points-v2 = <&cpu0_opp_table>;
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clock-latency = <300000>; /* From omap-cpufreq driver */
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cpu-idle-states = <&mpu_gate>;
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};
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idle-states {
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mpu_gate: mpu_gate {
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compatible = "arm,idle-state";
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entry-latency-us = <40>;
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exit-latency-us = <100>;
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min-residency-us = <300>;
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local-timer-stop;
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};
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};
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};
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cpu0_opp_table: opp-table {
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compatible = "operating-points-v2-ti-cpu";
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syscon = <&scm_conf>;
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opp50-300000000 {
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opp-hz = /bits/ 64 <300000000>;
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opp-microvolt = <950000 931000 969000>;
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opp-supported-hw = <0xFF 0x01>;
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opp-suspend;
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};
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opp100-600000000 {
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opp-hz = /bits/ 64 <600000000>;
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opp-microvolt = <1100000 1078000 1122000>;
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opp-supported-hw = <0xFF 0x04>;
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};
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opp120-720000000 {
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opp-hz = /bits/ 64 <720000000>;
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opp-microvolt = <1200000 1176000 1224000>;
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opp-supported-hw = <0xFF 0x08>;
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};
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oppturbo-800000000 {
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opp-hz = /bits/ 64 <800000000>;
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opp-microvolt = <1260000 1234800 1285200>;
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opp-supported-hw = <0xFF 0x10>;
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};
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oppnitro-1000000000 {
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opp-hz = /bits/ 64 <1000000000>;
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opp-microvolt = <1325000 1298500 1351500>;
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opp-supported-hw = <0xFF 0x20>;
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};
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};
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soc {
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compatible = "ti,omap-infra";
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};
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gic: interrupt-controller@48241000 {
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compatible = "arm,cortex-a9-gic";
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interrupt-controller;
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#interrupt-cells = <3>;
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reg = <0x48241000 0x1000>,
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<0x48240100 0x0100>;
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interrupt-parent = <&gic>;
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};
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wakeupgen: interrupt-controller@48281000 {
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compatible = "ti,omap4-wugen-mpu";
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interrupt-controller;
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#interrupt-cells = <3>;
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reg = <0x48281000 0x1000>;
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interrupt-parent = <&gic>;
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};
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scu: scu@48240000 {
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compatible = "arm,cortex-a9-scu";
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reg = <0x48240000 0x100>;
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};
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global_timer: timer@48240200 {
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compatible = "arm,cortex-a9-global-timer";
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reg = <0x48240200 0x100>;
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interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
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interrupt-parent = <&gic>;
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clocks = <&mpu_periphclk>;
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};
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local_timer: timer@48240600 {
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compatible = "arm,cortex-a9-twd-timer";
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reg = <0x48240600 0x100>;
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interrupts = <GIC_PPI 13 IRQ_TYPE_EDGE_RISING>;
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interrupt-parent = <&gic>;
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clocks = <&mpu_periphclk>;
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};
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cache-controller@48242000 {
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compatible = "arm,pl310-cache";
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reg = <0x48242000 0x1000>;
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cache-unified;
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cache-level = <2>;
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};
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ocp@44000000 {
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compatible = "simple-pm-bus";
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power-domains = <&prm_per>;
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clocks = <&l3_clkctrl AM4_L3_L3_MAIN_CLKCTRL 0>;
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clock-names = "fck";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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ti,no-idle;
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l3-noc@44000000 {
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compatible = "ti,am4372-l3-noc";
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reg = <0x44000000 0x400000>,
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<0x44800000 0x400000>;
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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};
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l4_wkup: interconnect@44c00000 {
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};
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l4_per: interconnect@48000000 {
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};
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l4_fast: interconnect@4a000000 {
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};
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target-module@4c000000 {
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compatible = "ti,sysc-omap4-simple", "ti,sysc";
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reg = <0x4c000000 0x4>;
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reg-names = "rev";
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clocks = <&emif_clkctrl AM4_EMIF_EMIF_CLKCTRL 0>;
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clock-names = "fck";
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ti,no-idle;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x4c000000 0x1000000>;
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emif: emif@0 {
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compatible = "ti,emif-am4372";
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reg = <0 0x1000000>;
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interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
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sram = <&pm_sram_code
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&pm_sram_data>;
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};
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};
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target-module@49000000 {
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compatible = "ti,sysc-omap4", "ti,sysc";
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reg = <0x49000000 0x4>;
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reg-names = "rev";
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clocks = <&l3_clkctrl AM4_L3_TPCC_CLKCTRL 0>;
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clock-names = "fck";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x49000000 0x10000>;
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edma: dma@0 {
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compatible = "ti,edma3-tpcc";
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reg = <0 0x10000>;
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reg-names = "edma3_cc";
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interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "edma3_ccint", "edma3_mperr",
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"edma3_ccerrint";
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dma-requests = <64>;
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#dma-cells = <2>;
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ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
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<&edma_tptc2 0>;
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ti,edma-memcpy-channels = <58 59>;
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};
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};
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target-module@49800000 {
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compatible = "ti,sysc-omap4", "ti,sysc";
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reg = <0x49800000 0x4>,
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<0x49800010 0x4>;
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reg-names = "rev", "sysc";
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ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
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ti,sysc-midle = <SYSC_IDLE_FORCE>;
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ti,sysc-sidle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_SMART>;
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clocks = <&l3_clkctrl AM4_L3_TPTC0_CLKCTRL 0>;
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clock-names = "fck";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x49800000 0x100000>;
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edma_tptc0: dma@0 {
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compatible = "ti,edma3-tptc";
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reg = <0 0x100000>;
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interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "edma3_tcerrint";
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};
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};
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target-module@49900000 {
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compatible = "ti,sysc-omap4", "ti,sysc";
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reg = <0x49900000 0x4>,
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<0x49900010 0x4>;
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reg-names = "rev", "sysc";
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ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
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ti,sysc-midle = <SYSC_IDLE_FORCE>;
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ti,sysc-sidle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_SMART>;
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clocks = <&l3_clkctrl AM4_L3_TPTC1_CLKCTRL 0>;
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clock-names = "fck";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x49900000 0x100000>;
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edma_tptc1: dma@0 {
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compatible = "ti,edma3-tptc";
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reg = <0 0x100000>;
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interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "edma3_tcerrint";
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};
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};
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target-module@49a00000 {
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compatible = "ti,sysc-omap4", "ti,sysc";
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reg = <0x49a00000 0x4>,
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<0x49a00010 0x4>;
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reg-names = "rev", "sysc";
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ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
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ti,sysc-midle = <SYSC_IDLE_FORCE>;
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ti,sysc-sidle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_SMART>;
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clocks = <&l3_clkctrl AM4_L3_TPTC2_CLKCTRL 0>;
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clock-names = "fck";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x49a00000 0x100000>;
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edma_tptc2: dma@0 {
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compatible = "ti,edma3-tptc";
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reg = <0 0x100000>;
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interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "edma3_tcerrint";
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};
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};
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target-module@47810000 {
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compatible = "ti,sysc-omap2", "ti,sysc";
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reg = <0x478102fc 0x4>,
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<0x47810110 0x4>,
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<0x47810114 0x4>;
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reg-names = "rev", "sysc", "syss";
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ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
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SYSC_OMAP2_ENAWAKEUP |
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SYSC_OMAP2_SOFTRESET |
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SYSC_OMAP2_AUTOIDLE)>;
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ti,sysc-sidle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_NO>,
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<SYSC_IDLE_SMART>;
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ti,syss-mask = <1>;
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clocks = <&l3s_clkctrl AM4_L3S_MMC3_CLKCTRL 0>;
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clock-names = "fck";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x47810000 0x1000>;
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mmc3: mmc@0 {
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compatible = "ti,am437-sdhci";
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ti,needs-special-reset;
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interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x0 0x1000>;
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status = "disabled";
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};
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};
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sham_target: target-module@53100000 {
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compatible = "ti,sysc-omap3-sham", "ti,sysc";
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reg = <0x53100100 0x4>,
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<0x53100110 0x4>,
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<0x53100114 0x4>;
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reg-names = "rev", "sysc", "syss";
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ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
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SYSC_OMAP2_AUTOIDLE)>;
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ti,sysc-sidle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_NO>,
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<SYSC_IDLE_SMART>;
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ti,syss-mask = <1>;
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/* Domains (P, C): per_pwrdm, l3_clkdm */
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clocks = <&l3_clkctrl AM4_L3_SHAM_CLKCTRL 0>;
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clock-names = "fck";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x53100000 0x1000>;
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sham: sham@0 {
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compatible = "ti,omap5-sham";
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reg = <0 0x300>;
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dmas = <&edma 36 0>;
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dma-names = "rx";
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interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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aes_target: target-module@53501000 {
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compatible = "ti,sysc-omap2", "ti,sysc";
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reg = <0x53501080 0x4>,
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<0x53501084 0x4>,
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<0x53501088 0x4>;
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reg-names = "rev", "sysc", "syss";
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ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
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SYSC_OMAP2_AUTOIDLE)>;
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ti,sysc-sidle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_NO>,
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<SYSC_IDLE_SMART>,
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<SYSC_IDLE_SMART_WKUP>;
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ti,syss-mask = <1>;
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/* Domains (P, C): per_pwrdm, l3_clkdm */
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clocks = <&l3_clkctrl AM4_L3_AES_CLKCTRL 0>;
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clock-names = "fck";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x53501000 0x1000>;
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aes: aes@0 {
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compatible = "ti,omap4-aes";
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reg = <0 0xa0>;
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interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&edma 6 0>,
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<&edma 5 0>;
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dma-names = "tx", "rx";
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};
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};
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des_target: target-module@53701000 {
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compatible = "ti,sysc-omap2", "ti,sysc";
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reg = <0x53701030 0x4>,
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<0x53701034 0x4>,
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<0x53701038 0x4>;
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reg-names = "rev", "sysc", "syss";
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ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
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SYSC_OMAP2_AUTOIDLE)>;
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ti,sysc-sidle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_NO>,
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<SYSC_IDLE_SMART>,
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<SYSC_IDLE_SMART_WKUP>;
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ti,syss-mask = <1>;
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/* Domains (P, C): per_pwrdm, l3_clkdm */
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clocks = <&l3_clkctrl AM4_L3_DES_CLKCTRL 0>;
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clock-names = "fck";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x53701000 0x1000>;
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des: des@0 {
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compatible = "ti,omap4-des";
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reg = <0 0xa0>;
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interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&edma 34 0>,
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<&edma 33 0>;
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dma-names = "tx", "rx";
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};
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};
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pruss_tm: target-module@54400000 {
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compatible = "ti,sysc-pruss", "ti,sysc";
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reg = <0x54426000 0x4>,
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<0x54426004 0x4>;
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reg-names = "rev", "sysc";
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ti,sysc-mask = <(SYSC_PRUSS_STANDBY_INIT |
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SYSC_PRUSS_SUB_MWAIT)>;
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ti,sysc-midle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_NO>,
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<SYSC_IDLE_SMART>;
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ti,sysc-sidle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_NO>,
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<SYSC_IDLE_SMART>;
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clocks = <&pruss_ocp_clkctrl AM4_PRUSS_OCP_PRUSS_CLKCTRL 0>;
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clock-names = "fck";
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resets = <&prm_per 1>;
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reset-names = "rstctrl";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x54400000 0x80000>;
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pruss1: pruss@0 {
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compatible = "ti,am4376-pruss1";
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reg = <0x0 0x40000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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pruss1_mem: memories@0 {
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reg = <0x0 0x2000>,
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<0x2000 0x2000>,
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<0x10000 0x8000>;
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reg-names = "dram0", "dram1",
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"shrdram2";
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};
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pruss1_cfg: cfg@26000 {
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compatible = "ti,pruss-cfg", "syscon";
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reg = <0x26000 0x2000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x26000 0x2000>;
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clocks {
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#address-cells = <1>;
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#size-cells = <0>;
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pruss1_iepclk_mux: iepclk-mux@30 {
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reg = <0x30>;
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#clock-cells = <0>;
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clocks = <&sysclk_div>, /* icss_iep_gclk */
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<&pruss_ocp_gclk>; /* icss_ocp_gclk */
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};
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};
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};
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pruss1_mii_rt: mii-rt@32000 {
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compatible = "ti,pruss-mii", "syscon";
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reg = <0x32000 0x58>;
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};
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pruss1_intc: interrupt-controller@20000 {
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compatible = "ti,pruss-intc";
|
|
reg = <0x20000 0x2000>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <3>;
|
|
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "host_intr0", "host_intr1",
|
|
"host_intr2", "host_intr3",
|
|
"host_intr4",
|
|
"host_intr6", "host_intr7";
|
|
ti,irqs-reserved = /bits/ 8 <0x20>; /* BIT(5) */
|
|
};
|
|
|
|
pru1_0: pru@34000 {
|
|
compatible = "ti,am4376-pru";
|
|
reg = <0x34000 0x3000>,
|
|
<0x22000 0x400>,
|
|
<0x22400 0x100>;
|
|
reg-names = "iram", "control", "debug";
|
|
firmware-name = "am437x-pru1_0-fw";
|
|
};
|
|
|
|
pru1_1: pru@38000 {
|
|
compatible = "ti,am4376-pru";
|
|
reg = <0x38000 0x3000>,
|
|
<0x24000 0x400>,
|
|
<0x24400 0x100>;
|
|
reg-names = "iram", "control", "debug";
|
|
firmware-name = "am437x-pru1_1-fw";
|
|
};
|
|
|
|
pruss1_mdio: mdio@32400 {
|
|
compatible = "ti,davinci_mdio";
|
|
reg = <0x32400 0x90>;
|
|
clocks = <&dpll_core_m4_ck>;
|
|
clock-names = "fck";
|
|
bus_freq = <1000000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
};
|
|
|
|
pruss0: pruss@40000 {
|
|
compatible = "ti,am4376-pruss0";
|
|
reg = <0x40000 0x40000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
|
|
pruss0_mem: memories@40000 {
|
|
reg = <0x40000 0x1000>,
|
|
<0x42000 0x1000>;
|
|
reg-names = "dram0", "dram1";
|
|
};
|
|
|
|
pruss0_cfg: cfg@66000 {
|
|
compatible = "ti,pruss-cfg", "syscon";
|
|
reg = <0x66000 0x2000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x66000 0x2000>;
|
|
|
|
clocks {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
pruss0_iepclk_mux: iepclk-mux@30 {
|
|
reg = <0x30>;
|
|
#clock-cells = <0>;
|
|
clocks = <&sysclk_div>, /* icss_iep_gclk */
|
|
<&pruss_ocp_gclk>; /* icss_ocp_gclk */
|
|
};
|
|
};
|
|
};
|
|
|
|
pruss0_mii_rt: mii-rt@72000 {
|
|
compatible = "ti,pruss-mii", "syscon";
|
|
reg = <0x72000 0x58>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pruss0_intc: interrupt-controller@60000 {
|
|
compatible = "ti,pruss-intc";
|
|
reg = <0x60000 0x2000>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <3>;
|
|
interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "host_intr0", "host_intr1",
|
|
"host_intr2", "host_intr3",
|
|
"host_intr4",
|
|
"host_intr6", "host_intr7";
|
|
ti,irqs-reserved = /bits/ 8 <0x20>; /* BIT(5) */
|
|
};
|
|
|
|
pru0_0: pru@74000 {
|
|
compatible = "ti,am4376-pru";
|
|
reg = <0x74000 0x1000>,
|
|
<0x62000 0x400>,
|
|
<0x62400 0x100>;
|
|
reg-names = "iram", "control", "debug";
|
|
firmware-name = "am437x-pru0_0-fw";
|
|
};
|
|
|
|
pru0_1: pru@78000 {
|
|
compatible = "ti,am4376-pru";
|
|
reg = <0x78000 0x1000>,
|
|
<0x64000 0x400>,
|
|
<0x64400 0x100>;
|
|
reg-names = "iram", "control", "debug";
|
|
firmware-name = "am437x-pru0_1-fw";
|
|
};
|
|
};
|
|
};
|
|
|
|
target-module@50000000 {
|
|
compatible = "ti,sysc-omap2", "ti,sysc";
|
|
reg = <0x50000000 4>,
|
|
<0x50000010 4>,
|
|
<0x50000014 4>;
|
|
reg-names = "rev", "sysc", "syss";
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>;
|
|
ti,syss-mask = <1>;
|
|
clocks = <&l3s_clkctrl AM4_L3S_GPMC_CLKCTRL 0>;
|
|
clock-names = "fck";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x50000000 0x50000000 0x00001000>, /* regs */
|
|
<0x00000000 0x00000000 0x40000000>; /* data */
|
|
|
|
gpmc: gpmc@50000000 {
|
|
compatible = "ti,am3352-gpmc";
|
|
dmas = <&edma 52 0>;
|
|
dma-names = "rxtx";
|
|
clocks = <&l3s_gclk>;
|
|
clock-names = "fck";
|
|
reg = <0x50000000 0x2000>;
|
|
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
|
|
gpmc,num-cs = <7>;
|
|
gpmc,num-waitpins = <2>;
|
|
#address-cells = <2>;
|
|
#size-cells = <1>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
target-module@47900000 {
|
|
compatible = "ti,sysc-omap4", "ti,sysc";
|
|
reg = <0x47900000 0x4>,
|
|
<0x47900010 0x4>;
|
|
reg-names = "rev", "sysc";
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>,
|
|
<SYSC_IDLE_SMART_WKUP>;
|
|
clocks = <&l3s_clkctrl AM4_L3S_QSPI_CLKCTRL 0>;
|
|
clock-names = "fck";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x47900000 0x1000>,
|
|
<0x30000000 0x30000000 0x4000000>;
|
|
|
|
qspi: spi@0 {
|
|
compatible = "ti,am4372-qspi";
|
|
reg = <0 0x100>,
|
|
<0x30000000 0x4000000>;
|
|
reg-names = "qspi_base", "qspi_mmap";
|
|
clocks = <&dpll_per_m2_div4_ck>;
|
|
clock-names = "fck";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <0 138 0x4>;
|
|
num-cs = <4>;
|
|
};
|
|
};
|
|
|
|
target-module@40300000 {
|
|
compatible = "ti,sysc-omap4-simple", "ti,sysc";
|
|
clocks = <&l3_clkctrl AM4_L3_OCMCRAM_CLKCTRL 0>;
|
|
clock-names = "fck";
|
|
ti,no-idle;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0 0x40300000 0x40000>;
|
|
|
|
ocmcram: sram@0 {
|
|
compatible = "mmio-sram";
|
|
reg = <0 0x40000>; /* 256k */
|
|
ranges = <0 0 0x40000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
pm_sram_code: pm-code-sram@0 {
|
|
compatible = "ti,sram";
|
|
reg = <0x0 0x1000>;
|
|
protect-exec;
|
|
};
|
|
|
|
pm_sram_data: pm-data-sram@1000 {
|
|
compatible = "ti,sram";
|
|
reg = <0x1000 0x1000>;
|
|
pool;
|
|
};
|
|
};
|
|
};
|
|
|
|
target-module@56000000 {
|
|
compatible = "ti,sysc-omap4", "ti,sysc";
|
|
reg = <0x5600fe00 0x4>,
|
|
<0x5600fe10 0x4>;
|
|
reg-names = "rev", "sysc";
|
|
ti,sysc-midle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>;
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>;
|
|
clocks = <&gfx_l3_clkctrl AM4_GFX_L3_GFX_CLKCTRL 0>;
|
|
clock-names = "fck";
|
|
power-domains = <&prm_gfx>;
|
|
resets = <&prm_gfx 0>;
|
|
reset-names = "rstctrl";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0 0x56000000 0x1000000>;
|
|
};
|
|
};
|
|
};
|
|
|
|
#include "am437x-l4.dtsi"
|
|
#include "am43xx-clocks.dtsi"
|
|
|
|
&prcm {
|
|
prm_mpu: prm@300 {
|
|
compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
|
|
reg = <0x300 0x100>;
|
|
#power-domain-cells = <0>;
|
|
};
|
|
|
|
prm_gfx: prm@400 {
|
|
compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
|
|
reg = <0x400 0x100>;
|
|
#power-domain-cells = <0>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
prm_rtc: prm@500 {
|
|
compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
|
|
reg = <0x500 0x100>;
|
|
#power-domain-cells = <0>;
|
|
};
|
|
|
|
prm_tamper: prm@600 {
|
|
compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
|
|
reg = <0x600 0x100>;
|
|
#power-domain-cells = <0>;
|
|
};
|
|
|
|
prm_cefuse: prm@700 {
|
|
compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
|
|
reg = <0x700 0x100>;
|
|
#power-domain-cells = <0>;
|
|
};
|
|
|
|
prm_per: prm@800 {
|
|
compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
|
|
reg = <0x800 0x100>;
|
|
#reset-cells = <1>;
|
|
#power-domain-cells = <0>;
|
|
};
|
|
|
|
prm_wkup: prm@2000 {
|
|
compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
|
|
reg = <0x2000 0x100>;
|
|
#reset-cells = <1>;
|
|
#power-domain-cells = <0>;
|
|
};
|
|
|
|
prm_device: prm@4000 {
|
|
compatible = "ti,am4-prm-inst", "ti,omap-prm-inst";
|
|
reg = <0x4000 0x100>;
|
|
#reset-cells = <1>;
|
|
};
|
|
};
|
|
|
|
/* Preferred always-on timer for clocksource */
|
|
&timer1_target {
|
|
ti,no-reset-on-init;
|
|
ti,no-idle;
|
|
clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_TIMER1_CLKCTRL 0>,
|
|
<&l4_wkup_clkctrl AM4_L4_WKUP_L4_WKUP_CLKCTRL 0>;
|
|
clock-names = "fck", "ick";
|
|
timer@0 {
|
|
assigned-clocks = <&timer1_fck>;
|
|
assigned-clock-parents = <&sys_clkin_ck>;
|
|
};
|
|
};
|
|
|
|
/* Preferred timer for clockevent */
|
|
&timer2_target {
|
|
ti,no-reset-on-init;
|
|
ti,no-idle;
|
|
clocks = <&l4ls_clkctrl AM4_L4LS_TIMER2_CLKCTRL 0>,
|
|
<&l4ls_clkctrl AM4_L4LS_L4_LS_CLKCTRL 0>;
|
|
clock-names = "fck", "ick";
|
|
timer@0 {
|
|
assigned-clocks = <&timer2_fck>;
|
|
assigned-clock-parents = <&sys_clkin_ck>;
|
|
};
|
|
};
|