113 lines
1.7 KiB
Plaintext
113 lines
1.7 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Device Tree file for Marvell Armada 382 reference board
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* (RD-AC3X-48G4X2XL)
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*
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* Copyright (C) 2020 Allied Telesis Labs
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*/
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/dts-v1/;
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#include "armada-385.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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/ {
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model = "Marvell Armada 382 RD-AC3X";
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compatible = "marvell,rd-ac3x-48g4x2xl", "marvell,rd-ac3x",
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"marvell,armada385", "marvell,armada380";
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chosen {
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stdout-path = "serial0:115200n8";
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};
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aliases {
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ethernet0 = ð1;
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};
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memory {
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device_type = "memory";
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reg = <0x00000000 0x20000000>; /* 512MB */
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};
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soc {
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ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
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MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
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};
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};
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&i2c0 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c0_pins>;
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status = "okay";
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eeprom@53{
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compatible = "atmel,24c64";
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reg = <0x53>;
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};
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/* CPLD device present at 0x3c. Function unknown */
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};
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&uart0 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_pins>;
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status = "okay";
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};
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ð1 {
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status = "okay";
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phy = <&phy0>;
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phy-mode = "rgmii-id";
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};
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&mdio {
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pinctrl-names = "default";
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pinctrl-0 = <&mdio_pins>;
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phy0: ethernet-phy@0 {
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reg = <0>;
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};
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};
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&pciec {
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status = "okay";
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};
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&pcie1 {
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/* Port 0, Lane 0 */
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status = "okay";
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};
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&nand_controller {
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status = "okay";
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nand@0 {
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reg = <0>;
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label = "pxa3xx_nand-0";
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nand-rb = <0>;
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nand-on-flash-bbt;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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reg = <0x00000000 0x00500000>;
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label = "u-boot";
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};
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partition@500000{
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reg = <0x00500000 0x00400000>;
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label = "u-boot env";
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};
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partition@900000{
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reg = <0x00900000 0x3F700000>;
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label = "user";
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};
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};
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};
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};
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&refclk {
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clock-frequency = <200000000>;
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};
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