652 lines
15 KiB
Plaintext
652 lines
15 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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//
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// Copyright (C) 2015 Freescale Semiconductor, Inc.
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#include <dt-bindings/media/video-interfaces.h>
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/ {
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chosen {
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stdout-path = &uart1;
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};
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memory@80000000 {
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device_type = "memory";
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reg = <0x80000000 0x20000000>;
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};
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backlight_display: backlight-display {
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compatible = "pwm-backlight";
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pwms = <&pwm1 0 5000000>;
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brightness-levels = <0 4 8 16 32 64 128 255>;
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default-brightness-level = <6>;
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status = "okay";
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};
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reg_sd1_vmmc: regulator-sd1-vmmc {
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compatible = "regulator-fixed";
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regulator-name = "VSD_3V3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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reg_peri_3v3: regulator-peri-3v3 {
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compatible = "regulator-fixed";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_peri_3v3>;
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regulator-name = "VPERI_3V3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio5 2 GPIO_ACTIVE_LOW>;
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/*
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* If you want to want to make this dynamic please
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* check schematics and test all affected peripherals:
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*
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* - sensors
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* - ethernet phy
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* - can
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* - bluetooth
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* - wm8960 audio codec
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* - ov5640 camera
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*/
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regulator-always-on;
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};
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reg_can_3v3: regulator-can-3v3 {
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compatible = "regulator-fixed";
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regulator-name = "can-3v3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpios = <&gpio_spi 3 GPIO_ACTIVE_LOW>;
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};
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sound-wm8960 {
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compatible = "fsl,imx-audio-wm8960";
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model = "wm8960-audio";
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audio-cpu = <&sai2>;
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audio-codec = <&codec>;
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audio-asrc = <&asrc>;
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hp-det-gpio = <&gpio5 4 0>;
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audio-routing =
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"Headphone Jack", "HP_L",
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"Headphone Jack", "HP_R",
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"Ext Spk", "SPK_LP",
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"Ext Spk", "SPK_LN",
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"Ext Spk", "SPK_RP",
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"Ext Spk", "SPK_RN",
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"LINPUT2", "Mic Jack",
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"LINPUT3", "Mic Jack",
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"RINPUT1", "AMIC",
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"RINPUT2", "AMIC",
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"Mic Jack", "MICB",
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"AMIC", "MICB";
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};
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spi-4 {
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compatible = "spi-gpio";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_spi4>;
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status = "okay";
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gpio-sck = <&gpio5 11 0>;
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gpio-mosi = <&gpio5 10 0>;
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cs-gpios = <&gpio5 7 GPIO_ACTIVE_LOW>;
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num-chipselects = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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gpio_spi: gpio@0 {
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compatible = "fairchild,74hc595";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0>;
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registers-number = <1>;
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spi-max-frequency = <100000>;
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enable-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
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};
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};
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panel {
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compatible = "innolux,at043tn24";
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backlight = <&backlight_display>;
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port {
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panel_in: endpoint {
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remote-endpoint = <&display_out>;
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};
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};
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};
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};
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&clks {
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assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
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assigned-clock-rates = <786432000>;
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};
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&i2c2 {
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c2>;
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status = "okay";
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codec: wm8960@1a {
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#sound-dai-cells = <0>;
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compatible = "wlf,wm8960";
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reg = <0x1a>;
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wlf,shared-lrclk;
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wlf,hp-cfg = <3 2 3>;
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wlf,gpio-cfg = <1 3>;
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clocks = <&clks IMX6UL_CLK_SAI2>;
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clock-names = "mclk";
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};
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camera@3c {
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compatible = "ovti,ov5640";
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reg = <0x3c>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_camera_clock>;
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clocks = <&clks IMX6UL_CLK_CSI>;
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clock-names = "xclk";
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powerdown-gpios = <&gpio_spi 6 GPIO_ACTIVE_HIGH>;
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reset-gpios = <&gpio_spi 5 GPIO_ACTIVE_LOW>;
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port {
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ov5640_to_parallel: endpoint {
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remote-endpoint = <¶llel_from_ov5640>;
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bus-width = <8>;
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data-shift = <2>; /* lines 9:2 are used */
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hsync-active = <0>;
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vsync-active = <0>;
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pclk-sample = <1>;
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};
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};
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};
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};
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&csi {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_csi1>;
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status = "okay";
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port {
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parallel_from_ov5640: endpoint {
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remote-endpoint = <&ov5640_to_parallel>;
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bus-type = <MEDIA_BUS_TYPE_PARALLEL>;
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};
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};
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};
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&fec1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_enet1>;
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phy-mode = "rmii";
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phy-handle = <ðphy0>;
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phy-supply = <®_peri_3v3>;
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status = "okay";
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};
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&fec2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_enet2>;
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phy-mode = "rmii";
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phy-handle = <ðphy1>;
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phy-supply = <®_peri_3v3>;
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy0: ethernet-phy@2 {
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compatible = "ethernet-phy-id0022.1560";
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reg = <2>;
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micrel,led-mode = <1>;
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clocks = <&clks IMX6UL_CLK_ENET_REF>;
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clock-names = "rmii-ref";
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};
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ethphy1: ethernet-phy@1 {
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compatible = "ethernet-phy-id0022.1560";
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reg = <1>;
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micrel,led-mode = <1>;
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clocks = <&clks IMX6UL_CLK_ENET2_REF>;
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clock-names = "rmii-ref";
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};
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};
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};
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&can1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_flexcan1>;
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xceiver-supply = <®_can_3v3>;
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status = "okay";
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};
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&can2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_flexcan2>;
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xceiver-supply = <®_can_3v3>;
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status = "okay";
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};
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&gpio_spi {
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eth0-phy-hog {
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gpio-hog;
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gpios = <1 GPIO_ACTIVE_HIGH>;
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output-high;
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line-name = "eth0-phy";
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};
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eth1-phy-hog {
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gpio-hog;
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gpios = <2 GPIO_ACTIVE_HIGH>;
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output-high;
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line-name = "eth1-phy";
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};
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};
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&i2c1 {
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1>;
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status = "okay";
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magnetometer@e {
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compatible = "fsl,mag3110";
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reg = <0x0e>;
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vdd-supply = <®_peri_3v3>;
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vddio-supply = <®_peri_3v3>;
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};
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};
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&lcdif {
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assigned-clocks = <&clks IMX6UL_CLK_LCDIF_PRE_SEL>;
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assigned-clock-parents = <&clks IMX6UL_CLK_PLL5_VIDEO_DIV>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_lcdif_dat
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&pinctrl_lcdif_ctrl>;
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status = "okay";
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port {
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display_out: endpoint {
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remote-endpoint = <&panel_in>;
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};
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};
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};
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&pwm1 {
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#pwm-cells = <2>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pwm1>;
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status = "okay";
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};
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&qspi {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_qspi>;
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status = "okay";
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flash0: flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "micron,n25q256a", "jedec,spi-nor";
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spi-max-frequency = <29000000>;
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spi-rx-bus-width = <4>;
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spi-tx-bus-width = <1>;
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reg = <0>;
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};
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};
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&sai2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_sai2>;
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assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>,
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<&clks IMX6UL_CLK_SAI2>;
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assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
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assigned-clock-rates = <0>, <12288000>;
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fsl,sai-mclk-direction-output;
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status = "okay";
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};
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&snvs_poweroff {
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status = "okay";
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};
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&snvs_pwrkey {
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status = "okay";
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};
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&tsc {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_tsc>;
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xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
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measure-delay-time = <0xffff>;
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pre-charge-time = <0xfff>;
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status = "okay";
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};
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&uart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1>;
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status = "okay";
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};
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&uart2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart2>;
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uart-has-rtscts;
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status = "okay";
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};
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&usbotg1 {
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dr_mode = "otg";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb_otg1>;
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status = "okay";
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};
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&usbotg2 {
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dr_mode = "host";
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disable-over-current;
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status = "okay";
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};
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&usbphy1 {
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fsl,tx-d-cal = <106>;
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};
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&usbphy2 {
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fsl,tx-d-cal = <106>;
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};
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&usdhc1 {
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc1>;
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pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
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pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
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cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
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keep-power-in-suspend;
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wakeup-source;
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vmmc-supply = <®_sd1_vmmc>;
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status = "okay";
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};
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&usdhc2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc2>;
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no-1-8-v;
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broken-cd;
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keep-power-in-suspend;
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wakeup-source;
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status = "okay";
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};
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&wdog1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_wdog>;
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fsl,ext-reset-output;
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};
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&iomuxc {
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pinctrl-names = "default";
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pinctrl_camera_clock: cameraclockgrp {
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fsl,pins = <
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MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x1b088
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>;
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};
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pinctrl_csi1: csi1grp {
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fsl,pins = <
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MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x1b088
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MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x1b088
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MX6UL_PAD_CSI_HSYNC__CSI_HSYNC 0x1b088
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MX6UL_PAD_CSI_DATA00__CSI_DATA02 0x1b088
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MX6UL_PAD_CSI_DATA01__CSI_DATA03 0x1b088
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MX6UL_PAD_CSI_DATA02__CSI_DATA04 0x1b088
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MX6UL_PAD_CSI_DATA03__CSI_DATA05 0x1b088
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MX6UL_PAD_CSI_DATA04__CSI_DATA06 0x1b088
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MX6UL_PAD_CSI_DATA05__CSI_DATA07 0x1b088
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MX6UL_PAD_CSI_DATA06__CSI_DATA08 0x1b088
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MX6UL_PAD_CSI_DATA07__CSI_DATA09 0x1b088
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>;
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};
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pinctrl_enet1: enet1grp {
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fsl,pins = <
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MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
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MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
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MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
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MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
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MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
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MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
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MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
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MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
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>;
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};
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pinctrl_enet2: enet2grp {
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fsl,pins = <
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MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
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MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
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MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
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MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
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MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
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MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
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MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
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MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
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MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
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MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031
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>;
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};
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pinctrl_flexcan1: flexcan1grp{
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fsl,pins = <
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MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020
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MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020
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>;
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};
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pinctrl_flexcan2: flexcan2grp{
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fsl,pins = <
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MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020
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MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020
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>;
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};
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pinctrl_i2c1: i2c1grp {
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fsl,pins = <
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MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
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MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
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>;
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};
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pinctrl_i2c2: i2c2grp {
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fsl,pins = <
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MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
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MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
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>;
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};
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pinctrl_lcdif_dat: lcdifdatgrp {
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fsl,pins = <
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MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79
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MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79
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MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79
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MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79
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MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79
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MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79
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MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79
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MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79
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MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79
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MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79
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MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79
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MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79
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MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79
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MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79
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MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79
|
|
MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79
|
|
MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79
|
|
MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79
|
|
MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79
|
|
MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79
|
|
MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79
|
|
MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79
|
|
MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79
|
|
MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79
|
|
>;
|
|
};
|
|
|
|
pinctrl_lcdif_ctrl: lcdifctrlgrp {
|
|
fsl,pins = <
|
|
MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79
|
|
MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79
|
|
MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79
|
|
MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79
|
|
/* used for lcd reset */
|
|
MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79
|
|
>;
|
|
};
|
|
|
|
pinctrl_qspi: qspigrp {
|
|
fsl,pins = <
|
|
MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1
|
|
MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1
|
|
MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1
|
|
MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1
|
|
MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1
|
|
MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1
|
|
>;
|
|
};
|
|
|
|
pinctrl_sai2: sai2grp {
|
|
fsl,pins = <
|
|
MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088
|
|
MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088
|
|
MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088
|
|
MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088
|
|
MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088
|
|
MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x17059
|
|
>;
|
|
};
|
|
|
|
pinctrl_peri_3v3: peri3v3grp {
|
|
fsl,pins = <
|
|
MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0
|
|
>;
|
|
};
|
|
|
|
pinctrl_pwm1: pwm1grp {
|
|
fsl,pins = <
|
|
MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x110b0
|
|
>;
|
|
};
|
|
|
|
pinctrl_sim2: sim2grp {
|
|
fsl,pins = <
|
|
MX6UL_PAD_CSI_DATA03__SIM2_PORT1_PD 0xb808
|
|
MX6UL_PAD_CSI_DATA04__SIM2_PORT1_CLK 0x31
|
|
MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B 0xb808
|
|
MX6UL_PAD_CSI_DATA06__SIM2_PORT1_SVEN 0xb808
|
|
MX6UL_PAD_CSI_DATA07__SIM2_PORT1_TRXD 0xb809
|
|
MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x3008
|
|
>;
|
|
};
|
|
|
|
pinctrl_spi4: spi4grp {
|
|
fsl,pins = <
|
|
MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x70a1
|
|
MX6UL_PAD_BOOT_MODE1__GPIO5_IO11 0x70a1
|
|
MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x70a1
|
|
MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x80000000
|
|
>;
|
|
};
|
|
|
|
pinctrl_tsc: tscgrp {
|
|
fsl,pins = <
|
|
MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0
|
|
MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0
|
|
MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
|
|
MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0
|
|
>;
|
|
};
|
|
|
|
pinctrl_uart1: uart1grp {
|
|
fsl,pins = <
|
|
MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
|
|
MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
|
|
>;
|
|
};
|
|
|
|
pinctrl_uart2: uart2grp {
|
|
fsl,pins = <
|
|
MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1
|
|
MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1
|
|
MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x1b0b1
|
|
MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x1b0b1
|
|
>;
|
|
};
|
|
|
|
pinctrl_usb_otg1: usbotg1grp {
|
|
fsl,pins = <
|
|
MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc1: usdhc1grp {
|
|
fsl,pins = <
|
|
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
|
|
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
|
|
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
|
|
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
|
|
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
|
|
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
|
|
MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */
|
|
MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */
|
|
MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 /* SD1 RESET */
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
|
|
fsl,pins = <
|
|
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
|
|
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
|
|
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
|
|
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
|
|
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
|
|
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
|
|
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
|
|
fsl,pins = <
|
|
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
|
|
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
|
|
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
|
|
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
|
|
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
|
|
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc2: usdhc2grp {
|
|
fsl,pins = <
|
|
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17059
|
|
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
|
|
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
|
|
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
|
|
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
|
|
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
|
|
>;
|
|
};
|
|
|
|
pinctrl_wdog: wdoggrp {
|
|
fsl,pins = <
|
|
MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0
|
|
>;
|
|
};
|
|
};
|