152 lines
2.6 KiB
Plaintext
152 lines
2.6 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2021 STMicroelectronics
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* Author: Alain Volmat <avolmat@me.com>
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*/
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/dts-v1/;
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#include "stih418.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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/ {
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model = "STiH418 B2264";
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compatible = "st,stih418-b2264", "st,stih418";
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chosen {
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stdout-path = &sbc_serial0;
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};
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memory@40000000 {
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device_type = "memory";
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reg = <0x40000000 0xc0000000>;
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};
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cpus {
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cpu@0 {
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operating-points-v2 = <&cpu_opp_table>;
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/* u-boot puts hpen in SBC dmem at 0xb8 offset */
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cpu-release-addr = <0x94100b8>;
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};
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cpu@1 {
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operating-points-v2 = <&cpu_opp_table>;
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/* u-boot puts hpen in SBC dmem at 0xb8 offset */
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cpu-release-addr = <0x94100b8>;
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};
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cpu@2 {
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operating-points-v2 = <&cpu_opp_table>;
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/* u-boot puts hpen in SBC dmem at 0xb8 offset */
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cpu-release-addr = <0x94100b8>;
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};
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cpu@3 {
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operating-points-v2 = <&cpu_opp_table>;
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/* u-boot puts hpen in SBC dmem at 0xb8 offset */
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cpu-release-addr = <0x94100b8>;
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};
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};
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cpu_opp_table: opp-table {
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compatible = "operating-points-v2";
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opp-shared;
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opp00 {
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opp-hz = /bits/ 64 <300000000>;
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opp-microvolt = <784000>;
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};
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opp01 {
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opp-hz = /bits/ 64 <500000000>;
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opp-microvolt = <784000>;
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};
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opp02 {
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opp-hz = /bits/ 64 <800000000>;
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opp-microvolt = <784000>;
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};
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opp03 {
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opp-hz = /bits/ 64 <1200000000>;
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opp-microvolt = <784000>;
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};
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opp04 {
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opp-hz = /bits/ 64 <1500000000>;
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opp-microvolt = <784000>;
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};
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};
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aliases {
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ttyAS0 = &sbc_serial0;
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ethernet0 = ðernet0;
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};
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soc {
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leds {
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compatible = "gpio-leds";
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led-green {
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gpios = <&pio1 3 GPIO_ACTIVE_HIGH>;
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default-state = "off";
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};
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};
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pin-controller-sbc@961f080 {
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gmac1 {
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rgmii1-0 {
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st,pins {
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rxd0 = <&pio1 4 ALT1 IN DE_IO 300 CLK_A>;
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rxd1 = <&pio1 5 ALT1 IN DE_IO 300 CLK_A>;
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rxd2 = <&pio1 6 ALT1 IN DE_IO 300 CLK_A>;
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rxd3 = <&pio1 7 ALT1 IN DE_IO 300 CLK_A>;
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rxdv = <&pio2 0 ALT1 IN DE_IO 300 CLK_A>;
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};
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};
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};
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};
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};
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};
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&ehci0 {
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status = "okay";
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};
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ðernet0 {
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phy-mode = "rgmii";
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pinctrl-0 = <&pinctrl_rgmii1 &pinctrl_rgmii1_mdio_1>;
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st,tx-retime-src = "clkgen";
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snps,reset-gpio = <&pio0 7 0>;
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snps,reset-active-low;
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snps,reset-delays-us = <0 10000 1000000>;
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status = "okay";
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};
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&miphy28lp_phy {
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phy_port0: port@9b22000 {
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st,sata-gen = <2>; /* SATA GEN3 */
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st,osc-rdy;
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};
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};
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&mmc0 {
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status = "okay";
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};
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&ohci1 {
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status = "okay";
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};
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&pwm1 {
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status = "okay";
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};
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&sata0 {
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status = "okay";
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};
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&sbc_serial0 {
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status = "okay";
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};
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&spifsm {
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status = "okay";
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};
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&st_dwc3 {
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status = "okay";
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};
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