145 lines
2.0 KiB
Plaintext
145 lines
2.0 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2021 Michael Walle <michael@walle.cc>
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*/
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/dts-v1/;
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/include/ "zynq-7000.dtsi"
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/ {
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model = "Ebang EBAZ4205";
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compatible = "ebang,ebaz4205", "xlnx,zynq-7000";
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aliases {
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ethernet0 = &gem0;
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serial0 = &uart1;
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};
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memory@0 {
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device_type = "memory";
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reg = <0x0 0x10000000>;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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};
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&clkc {
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ps-clk-frequency = <33333333>;
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fclk-enable = <8>;
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};
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&gem0 {
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status = "okay";
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phy-mode = "mii";
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phy-handle = <&phy>;
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/* PHY clock */
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assigned-clocks = <&clkc 18>;
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assigned-clock-rates = <25000000>;
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phy: ethernet-phy@0 {
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reg = <0>;
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};
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};
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&gpio0 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpio0_default>;
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};
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&nfc0 {
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status = "okay";
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nand@0 {
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reg = <0>;
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};
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};
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&pinctrl0 {
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pinctrl_gpio0_default: gpio0-default {
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mux {
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groups = "gpio0_20_grp", "gpio0_32_grp";
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function = "gpio0";
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};
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conf {
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groups = "gpio0_20_grp", "gpio0_32_grp";
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io-standard = <3>;
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slew-rate = <0>;
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};
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conf-pull-up {
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pins = "MIO20", "MIO32";
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bias-disable;
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};
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};
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pinctrl_sdhci0_default: sdhci0-default {
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mux {
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groups = "sdio0_2_grp";
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function = "sdio0";
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};
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conf {
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groups = "sdio0_2_grp";
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io-standard = <3>;
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slew-rate = <0>;
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bias-disable;
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};
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mux-cd {
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groups = "gpio0_34_grp";
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function = "sdio0_cd";
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};
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conf-cd {
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groups = "gpio0_34_grp";
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io-standard = <3>;
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slew-rate = <0>;
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bias-high-impedance;
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bias-pull-up;
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};
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};
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pinctrl_uart1_default: uart1-default {
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mux {
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groups = "uart1_4_grp";
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function = "uart1";
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};
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conf {
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groups = "uart1_4_grp";
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io-standard = <3>;
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slew-rate = <0>;
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};
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conf-rx {
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pins = "MIO25";
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bias-high-impedance;
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};
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conf-tx {
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pins = "MIO24";
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bias-disable;
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};
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};
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};
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&smcc {
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status = "okay";
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};
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&sdhci0 {
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status = "okay";
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disable-wp;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_sdhci0_default>;
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};
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&uart1 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1_default>;
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};
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