281 lines
6.0 KiB
C
281 lines
6.0 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* linux/arch/arm/mach-footbridge/common.c
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*
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* Copyright (C) 1998-2000 Russell King, Dave Gilbert.
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*/
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/mm.h>
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#include <linux/ioport.h>
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#include <linux/list.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/spinlock.h>
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#include <linux/dma-direct.h>
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#include <video/vga.h>
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#include <asm/page.h>
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#include <asm/irq.h>
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#include <asm/mach-types.h>
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#include <asm/setup.h>
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#include <asm/system_misc.h>
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#include <asm/hardware/dec21285.h>
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#include <asm/mach/irq.h>
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#include <asm/mach/map.h>
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#include <asm/mach/pci.h>
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#include "common.h"
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#include <mach/hardware.h>
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#include <mach/irqs.h>
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#include <asm/hardware/dec21285.h>
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static int dc21285_get_irq(void)
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{
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void __iomem *irqstatus = (void __iomem *)CSR_IRQ_STATUS;
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u32 mask = readl(irqstatus);
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if (mask & IRQ_MASK_SDRAMPARITY)
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return IRQ_SDRAMPARITY;
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if (mask & IRQ_MASK_UART_RX)
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return IRQ_CONRX;
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if (mask & IRQ_MASK_DMA1)
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return IRQ_DMA1;
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if (mask & IRQ_MASK_DMA2)
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return IRQ_DMA2;
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if (mask & IRQ_MASK_IN0)
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return IRQ_IN0;
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if (mask & IRQ_MASK_IN1)
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return IRQ_IN1;
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if (mask & IRQ_MASK_IN2)
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return IRQ_IN2;
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if (mask & IRQ_MASK_IN3)
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return IRQ_IN3;
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if (mask & IRQ_MASK_PCI)
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return IRQ_PCI;
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if (mask & IRQ_MASK_DOORBELLHOST)
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return IRQ_DOORBELLHOST;
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if (mask & IRQ_MASK_I2OINPOST)
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return IRQ_I2OINPOST;
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if (mask & IRQ_MASK_TIMER1)
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return IRQ_TIMER1;
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if (mask & IRQ_MASK_TIMER2)
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return IRQ_TIMER2;
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if (mask & IRQ_MASK_TIMER3)
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return IRQ_TIMER3;
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if (mask & IRQ_MASK_UART_TX)
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return IRQ_CONTX;
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if (mask & IRQ_MASK_PCI_ABORT)
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return IRQ_PCI_ABORT;
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if (mask & IRQ_MASK_PCI_SERR)
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return IRQ_PCI_SERR;
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if (mask & IRQ_MASK_DISCARD_TIMER)
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return IRQ_DISCARD_TIMER;
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if (mask & IRQ_MASK_PCI_DPERR)
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return IRQ_PCI_DPERR;
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if (mask & IRQ_MASK_PCI_PERR)
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return IRQ_PCI_PERR;
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return 0;
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}
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static void dc21285_handle_irq(struct pt_regs *regs)
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{
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int irq;
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do {
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irq = dc21285_get_irq();
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if (!irq)
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break;
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generic_handle_irq(irq);
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} while (1);
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}
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unsigned int mem_fclk_21285 = 50000000;
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EXPORT_SYMBOL(mem_fclk_21285);
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static int __init early_fclk(char *arg)
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{
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mem_fclk_21285 = simple_strtoul(arg, NULL, 0);
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return 0;
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}
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early_param("mem_fclk_21285", early_fclk);
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static int __init parse_tag_memclk(const struct tag *tag)
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{
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mem_fclk_21285 = tag->u.memclk.fmemclk;
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return 0;
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}
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__tagtable(ATAG_MEMCLK, parse_tag_memclk);
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/*
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* Footbridge IRQ translation table
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* Converts from our IRQ numbers into FootBridge masks
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*/
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static const int fb_irq_mask[] = {
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IRQ_MASK_UART_RX, /* 0 */
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IRQ_MASK_UART_TX, /* 1 */
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IRQ_MASK_TIMER1, /* 2 */
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IRQ_MASK_TIMER2, /* 3 */
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IRQ_MASK_TIMER3, /* 4 */
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IRQ_MASK_IN0, /* 5 */
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IRQ_MASK_IN1, /* 6 */
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IRQ_MASK_IN2, /* 7 */
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IRQ_MASK_IN3, /* 8 */
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IRQ_MASK_DOORBELLHOST, /* 9 */
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IRQ_MASK_DMA1, /* 10 */
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IRQ_MASK_DMA2, /* 11 */
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IRQ_MASK_PCI, /* 12 */
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IRQ_MASK_SDRAMPARITY, /* 13 */
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IRQ_MASK_I2OINPOST, /* 14 */
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IRQ_MASK_PCI_ABORT, /* 15 */
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IRQ_MASK_PCI_SERR, /* 16 */
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IRQ_MASK_DISCARD_TIMER, /* 17 */
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IRQ_MASK_PCI_DPERR, /* 18 */
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IRQ_MASK_PCI_PERR, /* 19 */
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};
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static void fb_mask_irq(struct irq_data *d)
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{
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*CSR_IRQ_DISABLE = fb_irq_mask[_DC21285_INR(d->irq)];
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}
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static void fb_unmask_irq(struct irq_data *d)
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{
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*CSR_IRQ_ENABLE = fb_irq_mask[_DC21285_INR(d->irq)];
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}
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static struct irq_chip fb_chip = {
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.irq_ack = fb_mask_irq,
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.irq_mask = fb_mask_irq,
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.irq_unmask = fb_unmask_irq,
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};
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static void __init __fb_init_irq(void)
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{
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unsigned int irq;
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/*
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* setup DC21285 IRQs
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*/
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*CSR_IRQ_DISABLE = -1;
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*CSR_FIQ_DISABLE = -1;
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for (irq = _DC21285_IRQ(0); irq < _DC21285_IRQ(20); irq++) {
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irq_set_chip_and_handler(irq, &fb_chip, handle_level_irq);
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irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE);
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}
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}
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void __init footbridge_init_irq(void)
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{
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set_handle_irq(dc21285_handle_irq);
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__fb_init_irq();
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if (machine_is_ebsa285())
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/* The following is dependent on which slot
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* you plug the Southbridge card into. We
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* currently assume that you plug it into
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* the right-hand most slot.
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*/
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isa_init_irq(IRQ_PCI);
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if (machine_is_netwinder())
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isa_init_irq(IRQ_IN3);
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}
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/*
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* Common mapping for all systems. Note that the outbound write flush is
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* commented out since there is a "No Fix" problem with it. Not mapping
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* it means that we have extra bullet protection on our feet.
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*/
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static struct map_desc ebsa285_host_io_desc[] __initdata = {
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{
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.virtual = ARMCSR_BASE,
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.pfn = __phys_to_pfn(DC21285_ARMCSR_BASE),
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.length = ARMCSR_SIZE,
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.type = MT_DEVICE,
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},
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{
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.virtual = PCIMEM_BASE,
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.pfn = __phys_to_pfn(DC21285_PCI_MEM),
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.length = PCIMEM_SIZE,
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.type = MT_DEVICE,
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}, {
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.virtual = PCICFG0_BASE,
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.pfn = __phys_to_pfn(DC21285_PCI_TYPE_0_CONFIG),
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.length = PCICFG0_SIZE,
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.type = MT_DEVICE,
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}, {
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.virtual = PCICFG1_BASE,
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.pfn = __phys_to_pfn(DC21285_PCI_TYPE_1_CONFIG),
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.length = PCICFG1_SIZE,
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.type = MT_DEVICE,
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}, {
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.virtual = PCIIACK_BASE,
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.pfn = __phys_to_pfn(DC21285_PCI_IACK),
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.length = PCIIACK_SIZE,
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.type = MT_DEVICE,
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},
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};
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void __init footbridge_map_io(void)
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{
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iotable_init(ebsa285_host_io_desc, ARRAY_SIZE(ebsa285_host_io_desc));
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pci_map_io_early(__phys_to_pfn(DC21285_PCI_IO));
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vga_base = PCIMEM_BASE;
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}
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void footbridge_restart(enum reboot_mode mode, const char *cmd)
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{
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if (mode == REBOOT_SOFT) {
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/* Jump into the ROM */
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soft_restart(0x41000000);
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} else {
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/*
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* Force the watchdog to do a CPU reset.
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*
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* After making sure that the watchdog is disabled
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* (so we can change the timer registers) we first
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* enable the timer to autoreload itself. Next, the
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* timer interval is set really short and any
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* current interrupt request is cleared (so we can
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* see an edge transition). Finally, TIMER4 is
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* enabled as the watchdog.
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*/
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*CSR_SA110_CNTL &= ~(1 << 13);
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*CSR_TIMER4_CNTL = TIMER_CNTL_ENABLE |
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TIMER_CNTL_AUTORELOAD |
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TIMER_CNTL_DIV16;
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*CSR_TIMER4_LOAD = 0x2;
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*CSR_TIMER4_CLR = 0;
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*CSR_SA110_CNTL |= (1 << 13);
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}
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}
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