166 lines
3.6 KiB
Plaintext
166 lines
3.6 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0 or MIT
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/*
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* Copyright (c) 2022, Arm Limited. All rights reserved.
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* Copyright (c) 2022, Linaro Limited. All rights reserved.
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*
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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interrupt-parent = <&gic>;
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#address-cells = <1>;
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#size-cells = <1>;
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aliases {
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serial0 = &uart0;
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serial1 = &uart1;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a35";
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reg = <0>;
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next-level-cache = <&L2_0>;
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};
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};
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memory@88200000 {
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device_type = "memory";
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reg = <0x88200000 0x77e00000>;
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};
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gic: interrupt-controller@1c000000 {
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compatible = "arm,gic-400";
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <0x1c010000 0x1000>,
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<0x1c02f000 0x2000>,
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<0x1c04f000 0x1000>,
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<0x1c06f000 0x2000>;
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) |
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IRQ_TYPE_LEVEL_LOW)>;
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};
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L2_0: l2-cache0 {
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compatible = "cache";
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cache-unified;
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cache-level = <2>;
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cache-size = <0x80000>;
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cache-line-size = <64>;
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cache-sets = <1024>;
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};
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refclk100mhz: refclk100mhz {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <100000000>;
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clock-output-names = "apb_pclk";
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};
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smbclk: refclk24mhzx2 {
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/* Reference 24MHz clock x 2 */
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <48000000>;
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clock-output-names = "smclk";
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) |
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IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) |
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IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) |
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IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) |
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IRQ_TYPE_LEVEL_LOW)>;
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};
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uartclk: uartclk {
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/* UART clock - 50MHz */
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <50000000>;
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clock-output-names = "uartclk";
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};
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psci {
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compatible = "arm,psci-1.0", "arm,psci-0.2";
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method = "smc";
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&gic>;
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ranges;
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timer@1a220000 {
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compatible = "arm,armv7-timer-mem";
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reg = <0x1a220000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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clock-frequency = <50000000>;
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ranges;
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frame@1a230000 {
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frame-number = <0>;
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interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x1a230000 0x1000>;
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};
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};
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uart0: serial@1a510000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x1a510000 0x1000>;
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interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&uartclk>, <&refclk100mhz>;
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clock-names = "uartclk", "apb_pclk";
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};
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uart1: serial@1a520000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x1a520000 0x1000>;
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interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&uartclk>, <&refclk100mhz>;
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clock-names = "uartclk", "apb_pclk";
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};
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mhu_hse1: mailbox@1b820000 {
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compatible = "arm,mhuv2-tx", "arm,primecell";
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reg = <0x1b820000 0x1000>;
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clocks = <&refclk100mhz>;
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clock-names = "apb_pclk";
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interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
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#mbox-cells = <2>;
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arm,mhuv2-protocols = <0 0>;
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secure-status = "okay"; /* secure-world-only */
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status = "disabled";
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};
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mhu_seh1: mailbox@1b830000 {
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compatible = "arm,mhuv2-rx", "arm,primecell";
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reg = <0x1b830000 0x1000>;
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clocks = <&refclk100mhz>;
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clock-names = "apb_pclk";
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interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
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#mbox-cells = <2>;
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arm,mhuv2-protocols = <0 0>;
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secure-status = "okay"; /* secure-world-only */
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status = "disabled";
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};
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};
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};
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