92 lines
1.6 KiB
Plaintext
92 lines
1.6 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Device Tree fragment for LS1028A QDS board, serdes 13bb
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*
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* Copyright 2019-2021 NXP
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*
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* Requires a LS1028A QDS board with lane B rework.
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* Requires a SCH-30841 card with lane A of connector rewired to PHY lane C.
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* Set-up is a SCH-30842 card in slot 1 and SCH-30841 in slot 2.
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*/
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/dts-v1/;
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/plugin/;
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&mdio_slot1 {
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#address-cells = <1>;
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#size-cells = <0>;
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slot1_sgmii: ethernet-phy@2 {
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/* AQR112 */
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reg = <0x2>;
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compatible = "ethernet-phy-ieee802.3-c45";
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};
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};
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&enetc_port0 {
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phy-handle = <&slot1_sgmii>;
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phy-mode = "usxgmii";
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managed = "in-band-status";
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status = "okay";
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};
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&mdio_slot2 {
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#address-cells = <1>;
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#size-cells = <0>;
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/* 4 ports on AQR412 */
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slot2_qxgmii0: ethernet-phy@0 {
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reg = <0x0>;
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compatible = "ethernet-phy-ieee802.3-c45";
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};
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slot2_qxgmii1: ethernet-phy@1 {
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reg = <0x1>;
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compatible = "ethernet-phy-ieee802.3-c45";
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};
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slot2_qxgmii2: ethernet-phy@2 {
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reg = <0x2>;
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compatible = "ethernet-phy-ieee802.3-c45";
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};
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slot2_qxgmii3: ethernet-phy@3 {
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reg = <0x3>;
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compatible = "ethernet-phy-ieee802.3-c45";
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};
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};
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&mscc_felix_ports {
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port@0 {
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status = "okay";
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phy-handle = <&slot2_qxgmii0>;
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phy-mode = "usxgmii";
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managed = "in-band-status";
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};
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port@1 {
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status = "okay";
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phy-handle = <&slot2_qxgmii1>;
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phy-mode = "usxgmii";
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managed = "in-band-status";
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};
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port@2 {
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status = "okay";
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phy-handle = <&slot2_qxgmii2>;
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phy-mode = "usxgmii";
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managed = "in-band-status";
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};
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port@3 {
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status = "okay";
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phy-handle = <&slot2_qxgmii3>;
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phy-mode = "usxgmii";
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managed = "in-band-status";
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};
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};
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&mscc_felix {
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status = "okay";
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};
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