147 lines
3.1 KiB
Plaintext
147 lines
3.1 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright 2018 Bang & Olufsen
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* Copyright 2022 Pengutronix
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*/
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/dts-v1/;
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#include "imx8mm-innocomm-wb15.dtsi"
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/ {
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model = "InnoComm WB15-EVK";
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compatible = "innocomm,wb15-evk", "fsl,imx8mm";
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chosen {
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stdout-path = &uart2;
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};
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leds {
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compatible = "gpio-leds";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpio_leds>;
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led-0 {
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label = "debug";
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gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>;
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default-state = "off";
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};
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};
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reg_vsd_3v3: regulator-vsd-3v3 {
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compatible = "regulator-fixed";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_reg_vsd_3v3>;
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regulator-name = "VSD_3V3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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reg_ethphy: regulator-eth-phy {
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compatible = "regulator-fixed";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec_phy_reg>;
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regulator-name = "PHY_3V3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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};
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&fec1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec>;
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phy-mode = "rgmii-id";
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phy-handle = <ðphy0>;
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fsl,magic-packet;
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy0: ethernet-phy@1 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <0x1>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec_phy>;
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reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
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phy-supply = <®_ethphy>;
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};
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};
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};
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&uart2 {
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status = "okay";
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};
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&usbotg1 {
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dr_mode = "otg";
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samsung,picophy-pre-emp-curr-control = <3>;
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samsung,picophy-dc-vol-level-adjust = <7>;
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disable-over-current;
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status = "okay";
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};
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&usbotg2 {
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dr_mode = "host";
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samsung,picophy-pre-emp-curr-control = <3>;
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samsung,picophy-dc-vol-level-adjust = <7>;
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disable-over-current;
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status = "okay";
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};
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&usdhc2 {
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cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
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vmmc-supply = <®_vsd_3v3>;
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status = "okay";
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};
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&iomuxc {
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pinctrl_fec: fec-grp {
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fsl,pins = <
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MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x03
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MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x03
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MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
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MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
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MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
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MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
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MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
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MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
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MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
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MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
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MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
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MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
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MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
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MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
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>;
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};
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pinctrl_fec_phy: fec-phy-grp {
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fsl,pins = <
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MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
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>;
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};
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pinctrl_fec_phy_reg: fec-phy-reg-grp {
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fsl,pins = <
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MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x16
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>;
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};
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pinctrl_gpio_leds: led-grp {
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fsl,pins = <
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MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0xd6
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>;
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};
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pinctrl_reg_vsd_3v3: reg-vsd-3v3-grp {
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fsl,pins = <
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MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
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>;
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};
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};
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