323 lines
7.0 KiB
Plaintext
323 lines
7.0 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2016 Freescale Semiconductor, Inc.
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* Copyright 2017-2020 NXP
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* Dong Aisheng <aisheng.dong@nxp.com>
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*/
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#include <dt-bindings/clock/imx8-clock.h>
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#include <dt-bindings/clock/imx8-lpcg.h>
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#include <dt-bindings/firmware/imx/rsrc.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/pinctrl/pads-imx8qxp.h>
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#include <dt-bindings/thermal/thermal.h>
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/ {
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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ethernet0 = &fec1;
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ethernet1 = &fec2;
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gpio0 = &lsio_gpio0;
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gpio1 = &lsio_gpio1;
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gpio2 = &lsio_gpio2;
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gpio3 = &lsio_gpio3;
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gpio4 = &lsio_gpio4;
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gpio5 = &lsio_gpio5;
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gpio6 = &lsio_gpio6;
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gpio7 = &lsio_gpio7;
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i2c0 = &i2c0;
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i2c1 = &i2c1;
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i2c2 = &i2c2;
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i2c3 = &i2c3;
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mmc0 = &usdhc1;
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mmc1 = &usdhc2;
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mmc2 = &usdhc3;
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mu0 = &lsio_mu0;
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mu1 = &lsio_mu1;
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mu2 = &lsio_mu2;
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mu3 = &lsio_mu3;
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mu4 = &lsio_mu4;
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serial0 = &lpuart0;
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serial1 = &lpuart1;
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serial2 = &lpuart2;
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serial3 = &lpuart3;
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vpu_core0 = &vpu_core0;
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vpu_core1 = &vpu_core1;
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vpu_core2 = &vpu_core2;
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};
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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/* We have 1 clusters with 4 Cortex-A35 cores */
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A35_0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a35";
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reg = <0x0 0x0>;
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enable-method = "psci";
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i-cache-size = <0x8000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <128>;
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next-level-cache = <&A35_L2>;
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clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
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operating-points-v2 = <&a35_opp_table>;
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#cooling-cells = <2>;
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};
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A35_1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a35";
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reg = <0x0 0x1>;
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enable-method = "psci";
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i-cache-size = <0x8000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <128>;
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next-level-cache = <&A35_L2>;
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clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
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operating-points-v2 = <&a35_opp_table>;
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#cooling-cells = <2>;
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};
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A35_2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a35";
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reg = <0x0 0x2>;
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enable-method = "psci";
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i-cache-size = <0x8000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <128>;
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next-level-cache = <&A35_L2>;
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clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
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operating-points-v2 = <&a35_opp_table>;
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#cooling-cells = <2>;
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};
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A35_3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a35";
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reg = <0x0 0x3>;
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enable-method = "psci";
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i-cache-size = <0x8000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <128>;
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next-level-cache = <&A35_L2>;
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clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
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operating-points-v2 = <&a35_opp_table>;
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#cooling-cells = <2>;
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};
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A35_L2: l2-cache0 {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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cache-size = <0x80000>;
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cache-line-size = <64>;
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cache-sets = <1024>;
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};
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};
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a35_opp_table: opp-table {
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compatible = "operating-points-v2";
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opp-shared;
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opp-900000000 {
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opp-hz = /bits/ 64 <900000000>;
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opp-microvolt = <1000000>;
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clock-latency-ns = <150000>;
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};
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opp-1200000000 {
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opp-hz = /bits/ 64 <1200000000>;
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opp-microvolt = <1100000>;
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clock-latency-ns = <150000>;
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opp-suspend;
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};
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};
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gic: interrupt-controller@51a00000 {
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compatible = "arm,gic-v3";
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reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
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<0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */
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#interrupt-cells = <3>;
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interrupt-controller;
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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decoder_boot: decoder-boot@84000000 {
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reg = <0 0x84000000 0 0x2000000>;
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no-map;
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};
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encoder_boot: encoder-boot@86000000 {
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reg = <0 0x86000000 0 0x200000>;
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no-map;
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};
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decoder_rpc: decoder-rpc@92000000 {
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reg = <0 0x92000000 0 0x100000>;
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no-map;
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};
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dsp_reserved: dsp@92400000 {
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reg = <0 0x92400000 0 0x2000000>;
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no-map;
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};
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encoder_rpc: encoder-rpc@94400000 {
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reg = <0 0x94400000 0 0x700000>;
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no-map;
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};
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};
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pmu {
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compatible = "arm,cortex-a35-pmu";
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interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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system-controller {
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compatible = "fsl,imx-scu";
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mbox-names = "tx0",
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"rx0",
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"gip3";
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mboxes = <&lsio_mu1 0 0
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&lsio_mu1 1 0
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&lsio_mu1 3 3>;
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pd: power-controller {
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compatible = "fsl,imx8qxp-scu-pd", "fsl,scu-pd";
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#power-domain-cells = <1>;
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};
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clk: clock-controller {
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compatible = "fsl,imx8qxp-clk", "fsl,scu-clk";
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#clock-cells = <2>;
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};
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iomuxc: pinctrl {
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compatible = "fsl,imx8qxp-iomuxc";
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};
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ocotp: ocotp {
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compatible = "fsl,imx8qxp-scu-ocotp";
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#address-cells = <1>;
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#size-cells = <1>;
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};
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scu_key: keys {
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compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key";
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linux,keycodes = <KEY_POWER>;
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status = "disabled";
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};
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rtc: rtc {
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compatible = "fsl,imx8qxp-sc-rtc";
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};
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watchdog {
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compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt";
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timeout-sec = <60>;
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};
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tsens: thermal-sensor {
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compatible = "fsl,imx8qxp-sc-thermal", "fsl,imx-sc-thermal";
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#thermal-sensor-cells = <1>;
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};
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
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<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
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<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */
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<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
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};
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xtal32k: clock-xtal32k {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32768>;
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clock-output-names = "xtal_32KHz";
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};
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xtal24m: clock-xtal24m {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <24000000>;
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clock-output-names = "xtal_24MHz";
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};
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thermal_zones: thermal-zones {
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cpu0-thermal {
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polling-delay-passive = <250>;
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polling-delay = <2000>;
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thermal-sensors = <&tsens IMX_SC_R_SYSTEM>;
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trips {
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cpu_alert0: trip0 {
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temperature = <107000>;
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hysteresis = <2000>;
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type = "passive";
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};
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cpu_crit0: trip1 {
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temperature = <127000>;
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hysteresis = <2000>;
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type = "critical";
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};
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};
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cooling-maps {
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map0 {
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trip = <&cpu_alert0>;
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cooling-device =
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<&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&A35_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&A35_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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};
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};
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};
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};
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/* sorted in register address */
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#include "imx8-ss-img.dtsi"
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#include "imx8-ss-vpu.dtsi"
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#include "imx8-ss-adma.dtsi"
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#include "imx8-ss-conn.dtsi"
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#include "imx8-ss-ddr.dtsi"
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#include "imx8-ss-lsio.dtsi"
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};
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#include "imx8qxp-ss-img.dtsi"
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#include "imx8qxp-ss-adma.dtsi"
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#include "imx8qxp-ss-conn.dtsi"
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#include "imx8qxp-ss-lsio.dtsi"
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