457 lines
8.1 KiB
Plaintext
457 lines
8.1 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/*
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* dtsi for Hisilicon Hi3660 Coresight
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*
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* Copyright (C) 2016-2018 HiSilicon Ltd.
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*
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* Author: Wanglai Shi <shiwanglai@hisilicon.com>
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*
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*/
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/ {
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soc {
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/* A53 cluster internals */
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etm@ecc40000 {
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compatible = "arm,coresight-etm4x", "arm,primecell";
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reg = <0 0xecc40000 0 0x1000>;
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clocks = <&crg_ctrl HI3660_PCLK>;
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clock-names = "apb_pclk";
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cpu = <&cpu0>;
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out-ports {
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port {
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etm0_out: endpoint {
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remote-endpoint =
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<&cluster0_funnel_in0>;
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};
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};
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};
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};
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etm@ecd40000 {
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compatible = "arm,coresight-etm4x", "arm,primecell";
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reg = <0 0xecd40000 0 0x1000>;
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clocks = <&crg_ctrl HI3660_PCLK>;
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clock-names = "apb_pclk";
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cpu = <&cpu1>;
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out-ports {
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port {
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etm1_out: endpoint {
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remote-endpoint =
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<&cluster0_funnel_in1>;
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};
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};
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};
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};
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etm@ece40000 {
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compatible = "arm,coresight-etm4x", "arm,primecell";
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reg = <0 0xece40000 0 0x1000>;
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clocks = <&crg_ctrl HI3660_PCLK>;
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clock-names = "apb_pclk";
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cpu = <&cpu2>;
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out-ports {
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port {
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etm2_out: endpoint {
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remote-endpoint =
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<&cluster0_funnel_in2>;
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};
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};
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};
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};
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etm@ecf40000 {
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compatible = "arm,coresight-etm4x", "arm,primecell";
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reg = <0 0xecf40000 0 0x1000>;
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clocks = <&crg_ctrl HI3660_PCLK>;
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clock-names = "apb_pclk";
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cpu = <&cpu3>;
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out-ports {
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port {
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etm3_out: endpoint {
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remote-endpoint =
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<&cluster0_funnel_in3>;
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};
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};
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};
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};
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funnel@ec801000 {
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compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
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reg = <0 0xec801000 0 0x1000>;
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clocks = <&crg_ctrl HI3660_PCLK>;
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clock-names = "apb_pclk";
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out-ports {
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port {
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cluster0_funnel_out: endpoint {
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remote-endpoint =
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<&cluster0_etf_in>;
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};
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};
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};
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in-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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cluster0_funnel_in0: endpoint {
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remote-endpoint = <&etm0_out>;
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};
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};
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port@1 {
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reg = <1>;
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cluster0_funnel_in1: endpoint {
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remote-endpoint = <&etm1_out>;
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};
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};
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port@2 {
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reg = <2>;
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cluster0_funnel_in2: endpoint {
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remote-endpoint = <&etm2_out>;
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};
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};
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port@3 {
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reg = <3>;
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cluster0_funnel_in3: endpoint {
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remote-endpoint = <&etm3_out>;
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};
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};
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};
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};
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etf@ec802000 {
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compatible = "arm,coresight-tmc", "arm,primecell";
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reg = <0 0xec802000 0 0x1000>;
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clocks = <&crg_ctrl HI3660_PCLK>;
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clock-names = "apb_pclk";
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in-ports {
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port {
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cluster0_etf_in: endpoint {
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remote-endpoint =
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<&cluster0_funnel_out>;
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};
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};
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};
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out-ports {
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port {
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cluster0_etf_out: endpoint {
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remote-endpoint =
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<&combo_funnel_in0>;
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};
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};
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};
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};
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/* A73 cluster internals */
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etm@ed440000 {
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compatible = "arm,coresight-etm4x", "arm,primecell";
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reg = <0 0xed440000 0 0x1000>;
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clocks = <&crg_ctrl HI3660_PCLK>;
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clock-names = "apb_pclk";
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cpu = <&cpu4>;
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out-ports {
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port {
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etm4_out: endpoint {
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remote-endpoint =
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<&cluster1_funnel_in0>;
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};
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};
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};
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};
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etm@ed540000 {
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compatible = "arm,coresight-etm4x", "arm,primecell";
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reg = <0 0xed540000 0 0x1000>;
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clocks = <&crg_ctrl HI3660_PCLK>;
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clock-names = "apb_pclk";
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cpu = <&cpu5>;
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out-ports {
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port {
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etm5_out: endpoint {
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remote-endpoint =
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<&cluster1_funnel_in1>;
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};
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};
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};
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};
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etm@ed640000 {
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compatible = "arm,coresight-etm4x", "arm,primecell";
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reg = <0 0xed640000 0 0x1000>;
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clocks = <&crg_ctrl HI3660_PCLK>;
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clock-names = "apb_pclk";
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cpu = <&cpu6>;
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out-ports {
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port {
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etm6_out: endpoint {
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remote-endpoint =
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<&cluster1_funnel_in2>;
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};
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};
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};
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};
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etm@ed740000 {
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compatible = "arm,coresight-etm4x", "arm,primecell";
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reg = <0 0xed740000 0 0x1000>;
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clocks = <&crg_ctrl HI3660_PCLK>;
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clock-names = "apb_pclk";
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cpu = <&cpu7>;
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out-ports {
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port {
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etm7_out: endpoint {
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remote-endpoint =
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<&cluster1_funnel_in3>;
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};
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};
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};
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};
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funnel@ed001000 {
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compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
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reg = <0 0xed001000 0 0x1000>;
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clocks = <&crg_ctrl HI3660_PCLK>;
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clock-names = "apb_pclk";
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out-ports {
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port {
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cluster1_funnel_out: endpoint {
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remote-endpoint =
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<&cluster1_etf_in>;
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};
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};
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};
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in-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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cluster1_funnel_in0: endpoint {
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remote-endpoint = <&etm4_out>;
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};
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};
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port@1 {
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reg = <1>;
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cluster1_funnel_in1: endpoint {
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remote-endpoint = <&etm5_out>;
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};
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};
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port@2 {
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reg = <2>;
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cluster1_funnel_in2: endpoint {
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remote-endpoint = <&etm6_out>;
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};
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};
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port@3 {
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reg = <3>;
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cluster1_funnel_in3: endpoint {
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remote-endpoint = <&etm7_out>;
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};
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};
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};
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};
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etf@ed002000 {
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compatible = "arm,coresight-tmc", "arm,primecell";
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reg = <0 0xed002000 0 0x1000>;
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clocks = <&crg_ctrl HI3660_PCLK>;
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clock-names = "apb_pclk";
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in-ports {
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port {
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cluster1_etf_in: endpoint {
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remote-endpoint =
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<&cluster1_funnel_out>;
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};
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};
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};
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out-ports {
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port {
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cluster1_etf_out: endpoint {
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remote-endpoint =
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<&combo_funnel_in1>;
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};
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};
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};
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};
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/* An invisible combo funnel between clusters and top funnel */
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funnel {
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compatible = "arm,coresight-static-funnel";
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clocks = <&crg_ctrl HI3660_PCLK>;
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clock-names = "apb_pclk";
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out-ports {
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port {
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combo_funnel_out: endpoint {
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remote-endpoint =
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<&top_funnel_in>;
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};
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};
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};
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in-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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combo_funnel_in0: endpoint {
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remote-endpoint =
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<&cluster0_etf_out>;
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};
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};
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port@1 {
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reg = <1>;
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combo_funnel_in1: endpoint {
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remote-endpoint =
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<&cluster1_etf_out>;
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};
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};
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};
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};
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/* Top internals */
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funnel@ec031000 {
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compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
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reg = <0 0xec031000 0 0x1000>;
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clocks = <&crg_ctrl HI3660_PCLK>;
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clock-names = "apb_pclk";
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out-ports {
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port {
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top_funnel_out: endpoint {
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remote-endpoint =
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<&top_etf_in>;
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};
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};
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};
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in-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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top_funnel_in: endpoint {
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remote-endpoint =
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<&combo_funnel_out>;
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};
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};
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};
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};
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etf@ec036000 {
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compatible = "arm,coresight-tmc", "arm,primecell";
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reg = <0 0xec036000 0 0x1000>;
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clocks = <&crg_ctrl HI3660_PCLK>;
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clock-names = "apb_pclk";
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in-ports {
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port {
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top_etf_in: endpoint {
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remote-endpoint =
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<&top_funnel_out>;
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};
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};
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};
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out-ports {
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port {
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top_etf_out: endpoint {
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remote-endpoint =
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<&replicator_in>;
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};
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};
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};
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};
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replicator {
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compatible = "arm,coresight-static-replicator";
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clocks = <&crg_ctrl HI3660_PCLK>;
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clock-names = "apb_pclk";
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in-ports {
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port {
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replicator_in: endpoint {
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remote-endpoint =
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<&top_etf_out>;
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};
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};
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};
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out-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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replicator0_out0: endpoint {
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remote-endpoint = <&etr_in>;
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};
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};
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port@1 {
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reg = <1>;
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replicator0_out1: endpoint {
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remote-endpoint = <&tpiu_in>;
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};
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};
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};
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};
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etr@ec033000 {
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compatible = "arm,coresight-tmc", "arm,primecell";
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reg = <0 0xec033000 0 0x1000>;
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clocks = <&crg_ctrl HI3660_PCLK>;
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clock-names = "apb_pclk";
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in-ports {
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port {
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etr_in: endpoint {
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remote-endpoint =
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<&replicator0_out0>;
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};
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};
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};
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};
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tpiu@ec032000 {
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compatible = "arm,coresight-tpiu", "arm,primecell";
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reg = <0 0xec032000 0 0x1000>;
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clocks = <&crg_ctrl HI3660_PCLK>;
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clock-names = "apb_pclk";
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in-ports {
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port {
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tpiu_in: endpoint {
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remote-endpoint =
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<&replicator0_out1>;
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};
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};
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};
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};
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};
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};
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