1231 lines
31 KiB
Plaintext
1231 lines
31 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/*
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* SDM670 SoC device tree source, adapted from SDM845 SoC device tree
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*
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* Copyright (c) 2018, The Linux Foundation. All rights reserved.
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* Copyright (c) 2022, Richard Acayan. All rights reserved.
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*/
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#include <dt-bindings/clock/qcom,gcc-sdm845.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/dma/qcom-gpi.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/phy/phy-qcom-qusb2.h>
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#include <dt-bindings/power/qcom-rpmpd.h>
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#include <dt-bindings/soc/qcom,rpmh-rsc.h>
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/ {
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interrupt-parent = <&intc>;
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#address-cells = <2>;
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#size-cells = <2>;
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aliases { };
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chosen { };
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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CPU0: cpu@0 {
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device_type = "cpu";
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compatible = "qcom,kryo360";
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reg = <0x0 0x0>;
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enable-method = "psci";
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power-domains = <&CPU_PD0>;
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power-domain-names = "psci";
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next-level-cache = <&L2_0>;
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L2_0: l2-cache {
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compatible = "cache";
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next-level-cache = <&L3_0>;
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L3_0: l3-cache {
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compatible = "cache";
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};
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};
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};
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CPU1: cpu@100 {
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device_type = "cpu";
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compatible = "qcom,kryo360";
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reg = <0x0 0x100>;
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enable-method = "psci";
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power-domains = <&CPU_PD1>;
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power-domain-names = "psci";
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next-level-cache = <&L2_100>;
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L2_100: l2-cache {
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compatible = "cache";
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next-level-cache = <&L3_0>;
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};
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};
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CPU2: cpu@200 {
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device_type = "cpu";
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compatible = "qcom,kryo360";
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reg = <0x0 0x200>;
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enable-method = "psci";
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power-domains = <&CPU_PD2>;
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power-domain-names = "psci";
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next-level-cache = <&L2_200>;
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L2_200: l2-cache {
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compatible = "cache";
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next-level-cache = <&L3_0>;
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};
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};
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CPU3: cpu@300 {
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device_type = "cpu";
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compatible = "qcom,kryo360";
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reg = <0x0 0x300>;
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enable-method = "psci";
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power-domains = <&CPU_PD3>;
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power-domain-names = "psci";
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next-level-cache = <&L2_300>;
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L2_300: l2-cache {
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compatible = "cache";
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next-level-cache = <&L3_0>;
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};
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};
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CPU4: cpu@400 {
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device_type = "cpu";
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compatible = "qcom,kryo360";
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reg = <0x0 0x400>;
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enable-method = "psci";
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power-domains = <&CPU_PD4>;
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power-domain-names = "psci";
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next-level-cache = <&L2_400>;
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L2_400: l2-cache {
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compatible = "cache";
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next-level-cache = <&L3_0>;
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};
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};
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CPU5: cpu@500 {
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device_type = "cpu";
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compatible = "qcom,kryo360";
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reg = <0x0 0x500>;
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enable-method = "psci";
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power-domains = <&CPU_PD5>;
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power-domain-names = "psci";
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next-level-cache = <&L2_500>;
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L2_500: l2-cache {
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compatible = "cache";
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next-level-cache = <&L3_0>;
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};
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};
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CPU6: cpu@600 {
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device_type = "cpu";
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compatible = "qcom,kryo360";
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reg = <0x0 0x600>;
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enable-method = "psci";
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power-domains = <&CPU_PD6>;
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power-domain-names = "psci";
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next-level-cache = <&L2_600>;
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L2_600: l2-cache {
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compatible = "cache";
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next-level-cache = <&L3_0>;
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};
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};
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CPU7: cpu@700 {
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device_type = "cpu";
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compatible = "qcom,kryo360";
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reg = <0x0 0x700>;
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enable-method = "psci";
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power-domains = <&CPU_PD7>;
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power-domain-names = "psci";
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next-level-cache = <&L2_700>;
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L2_700: l2-cache {
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compatible = "cache";
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next-level-cache = <&L3_0>;
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};
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};
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&CPU0>;
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};
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core1 {
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cpu = <&CPU1>;
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};
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core2 {
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cpu = <&CPU2>;
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};
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core3 {
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cpu = <&CPU3>;
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};
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core4 {
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cpu = <&CPU4>;
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};
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core5 {
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cpu = <&CPU5>;
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};
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core6 {
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cpu = <&CPU6>;
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};
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core7 {
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cpu = <&CPU7>;
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};
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};
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};
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idle-states {
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entry-method = "psci";
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LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
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compatible = "arm,idle-state";
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idle-state-name = "little-rail-power-collapse";
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arm,psci-suspend-param = <0x40000004>;
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entry-latency-us = <702>;
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exit-latency-us = <915>;
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min-residency-us = <1617>;
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local-timer-stop;
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};
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BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
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compatible = "arm,idle-state";
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idle-state-name = "big-rail-power-collapse";
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arm,psci-suspend-param = <0x40000004>;
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entry-latency-us = <526>;
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exit-latency-us = <1854>;
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min-residency-us = <2380>;
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local-timer-stop;
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};
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};
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domain-idle-states {
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CLUSTER_SLEEP_0: cluster-sleep-0 {
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compatible = "domain-idle-state";
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arm,psci-suspend-param = <0x4100c244>;
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entry-latency-us = <3263>;
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exit-latency-us = <6562>;
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min-residency-us = <9825>;
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};
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};
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};
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firmware {
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scm {
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compatible = "qcom,scm-sdm670", "qcom,scm";
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};
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};
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memory@80000000 {
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device_type = "memory";
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/* We expect the bootloader to fill in the size */
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reg = <0x0 0x80000000 0x0 0x0>;
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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CPU_PD0: power-domain-cpu0 {
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#power-domain-cells = <0>;
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power-domains = <&CLUSTER_PD>;
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domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
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};
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CPU_PD1: power-domain-cpu1 {
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#power-domain-cells = <0>;
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power-domains = <&CLUSTER_PD>;
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domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
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};
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CPU_PD2: power-domain-cpu2 {
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#power-domain-cells = <0>;
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power-domains = <&CLUSTER_PD>;
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domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
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};
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CPU_PD3: power-domain-cpu3 {
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#power-domain-cells = <0>;
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power-domains = <&CLUSTER_PD>;
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domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
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};
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CPU_PD4: power-domain-cpu4 {
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#power-domain-cells = <0>;
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power-domains = <&CLUSTER_PD>;
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domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
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};
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CPU_PD5: power-domain-cpu5 {
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#power-domain-cells = <0>;
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power-domains = <&CLUSTER_PD>;
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domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
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};
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CPU_PD6: power-domain-cpu6 {
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#power-domain-cells = <0>;
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power-domains = <&CLUSTER_PD>;
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domain-idle-states = <&BIG_CPU_SLEEP_0>;
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};
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CPU_PD7: power-domain-cpu7 {
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#power-domain-cells = <0>;
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power-domains = <&CLUSTER_PD>;
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domain-idle-states = <&BIG_CPU_SLEEP_0>;
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};
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CLUSTER_PD: power-domain-cluster {
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#power-domain-cells = <0>;
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domain-idle-states = <&CLUSTER_SLEEP_0>;
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};
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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hyp_mem: hyp-mem@85700000 {
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reg = <0 0x85700000 0 0x600000>;
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no-map;
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};
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xbl_mem: xbl-mem@85e00000 {
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reg = <0 0x85e00000 0 0x100000>;
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no-map;
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};
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aop_mem: aop-mem@85fc0000 {
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reg = <0 0x85fc0000 0 0x20000>;
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no-map;
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};
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aop_cmd_db_mem: aop-cmd-db-mem@85fe0000 {
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compatible = "qcom,cmd-db";
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reg = <0 0x85fe0000 0 0x20000>;
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no-map;
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};
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camera_mem: camera-mem@8ab00000 {
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reg = <0 0x8ab00000 0 0x500000>;
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no-map;
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};
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mpss_region: mpss@8b000000 {
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reg = <0 0x8b000000 0 0x7e00000>;
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no-map;
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};
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venus_mem: venus@92e00000 {
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reg = <0 0x92e00000 0 0x500000>;
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no-map;
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};
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wlan_msa_mem: wlan-msa@93300000 {
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reg = <0 0x93300000 0 0x100000>;
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no-map;
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};
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cdsp_mem: cdsp@93400000 {
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reg = <0 0x93400000 0 0x800000>;
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no-map;
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};
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mba_region: mba@93c00000 {
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reg = <0 0x93c00000 0 0x200000>;
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no-map;
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};
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adsp_mem: adsp@93e00000 {
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reg = <0 0x93e00000 0 0x1e00000>;
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no-map;
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};
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ipa_fw_mem: ipa-fw@95c00000 {
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reg = <0 0x95c00000 0 0x10000>;
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no-map;
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};
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ipa_gsi_mem: ipa-gsi@95c10000 {
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reg = <0 0x95c10000 0 0x5000>;
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no-map;
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};
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gpu_mem: gpu@95c15000 {
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reg = <0 0x95c15000 0 0x2000>;
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no-map;
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};
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spss_mem: spss@97b00000 {
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reg = <0 0x97b00000 0 0x100000>;
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no-map;
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};
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qseecom_mem: qseecom@9e400000 {
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reg = <0 0x9e400000 0 0x1400000>;
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no-map;
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};
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
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};
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soc: soc@0 {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0 0 0 0 0x10 0>;
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dma-ranges = <0 0 0 0 0x10 0>;
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compatible = "simple-bus";
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gcc: clock-controller@100000 {
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compatible = "qcom,gcc-sdm670";
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reg = <0 0x00100000 0 0x1f0000>;
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clocks = <&rpmhcc RPMH_CXO_CLK>,
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<&rpmhcc RPMH_CXO_CLK_A>,
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<&sleep_clk>;
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clock-names = "bi_tcxo",
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"bi_tcxo_ao",
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"sleep_clk";
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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};
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qfprom: qfprom@784000 {
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compatible = "qcom,sdm670-qfprom", "qcom,qfprom";
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reg = <0 0x00784000 0 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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qusb2_hstx_trim: hstx-trim@1eb {
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reg = <0x1eb 0x1>;
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bits = <1 4>;
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};
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};
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sdhc_1: mmc@7c4000 {
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compatible = "qcom,sdm670-sdhci", "qcom,sdhci-msm-v5";
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reg = <0 0x007c4000 0 0x1000>,
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<0 0x007c5000 0 0x1000>,
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<0 0x007c8000 0 0x8000>;
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reg-names = "hc", "cqhci", "ice";
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interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "hc_irq", "pwr_irq";
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clocks = <&gcc GCC_SDCC1_AHB_CLK>,
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<&gcc GCC_SDCC1_APPS_CLK>,
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<&rpmhcc RPMH_CXO_CLK>,
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<&gcc GCC_SDCC1_ICE_CORE_CLK>,
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<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>;
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clock-names = "iface", "core", "xo", "ice", "bus";
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iommus = <&apps_smmu 0x140 0xf>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&sdc1_state_on>;
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pinctrl-1 = <&sdc1_state_off>;
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power-domains = <&rpmhpd SDM670_CX>;
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bus-width = <8>;
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non-removable;
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status = "disabled";
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};
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gpi_dma0: dma-controller@800000 {
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#dma-cells = <3>;
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compatible = "qcom,sdm670-gpi-dma", "qcom,sdm845-gpi-dma";
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reg = <0 0x00800000 0 0x60000>;
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interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
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dma-channels = <13>;
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dma-channel-mask = <0xfa>;
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iommus = <&apps_smmu 0x16 0x0>;
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status = "disabled";
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};
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qupv3_id_0: geniqup@8c0000 {
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compatible = "qcom,geni-se-qup";
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reg = <0 0x008c0000 0 0x6000>;
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clock-names = "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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iommus = <&apps_smmu 0x3 0x0>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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status = "disabled";
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i2c0: i2c@880000 {
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compatible = "qcom,geni-i2c";
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reg = <0 0x00880000 0 0x4000>;
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clock-names = "se";
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clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
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pinctrl-names = "default";
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pinctrl-0 = <&qup_i2c0_default>;
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interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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power-domains = <&rpmhpd SDM670_CX>;
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dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
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<&gpi_dma0 1 0 QCOM_GPI_I2C>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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i2c1: i2c@884000 {
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compatible = "qcom,geni-i2c";
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reg = <0 0x00884000 0 0x4000>;
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clock-names = "se";
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clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
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pinctrl-names = "default";
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pinctrl-0 = <&qup_i2c1_default>;
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interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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power-domains = <&rpmhpd SDM670_CX>;
|
|
dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
|
|
<&gpi_dma0 1 1 QCOM_GPI_I2C>;
|
|
dma-names = "tx", "rx";
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c2: i2c@888000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0 0x00888000 0 0x4000>;
|
|
clock-names = "se";
|
|
clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&qup_i2c2_default>;
|
|
interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
power-domains = <&rpmhpd SDM670_CX>;
|
|
dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
|
|
<&gpi_dma0 1 2 QCOM_GPI_I2C>;
|
|
dma-names = "tx", "rx";
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c3: i2c@88c000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0 0x0088c000 0 0x4000>;
|
|
clock-names = "se";
|
|
clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&qup_i2c3_default>;
|
|
interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
power-domains = <&rpmhpd SDM670_CX>;
|
|
dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
|
|
<&gpi_dma0 1 3 QCOM_GPI_I2C>;
|
|
dma-names = "tx", "rx";
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c4: i2c@890000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0 0x00890000 0 0x4000>;
|
|
clock-names = "se";
|
|
clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&qup_i2c4_default>;
|
|
interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
power-domains = <&rpmhpd SDM670_CX>;
|
|
dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
|
|
<&gpi_dma0 1 4 QCOM_GPI_I2C>;
|
|
dma-names = "tx", "rx";
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c5: i2c@894000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0 0x00894000 0 0x4000>;
|
|
clock-names = "se";
|
|
clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&qup_i2c5_default>;
|
|
interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
power-domains = <&rpmhpd SDM670_CX>;
|
|
dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
|
|
<&gpi_dma0 1 5 QCOM_GPI_I2C>;
|
|
dma-names = "tx", "rx";
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c6: i2c@898000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0 0x00898000 0 0x4000>;
|
|
clock-names = "se";
|
|
clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&qup_i2c6_default>;
|
|
interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
power-domains = <&rpmhpd SDM670_CX>;
|
|
dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
|
|
<&gpi_dma0 1 6 QCOM_GPI_I2C>;
|
|
dma-names = "tx", "rx";
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c7: i2c@89c000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0 0x0089c000 0 0x4000>;
|
|
clock-names = "se";
|
|
clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&qup_i2c7_default>;
|
|
interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
power-domains = <&rpmhpd SDM670_CX>;
|
|
dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
|
|
<&gpi_dma0 1 7 QCOM_GPI_I2C>;
|
|
dma-names = "tx", "rx";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
gpi_dma1: dma-controller@a00000 {
|
|
#dma-cells = <3>;
|
|
compatible = "qcom,sdm670-gpi-dma", "qcom,sdm845-gpi-dma";
|
|
reg = <0 0x00a00000 0 0x60000>;
|
|
interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
|
|
dma-channels = <13>;
|
|
dma-channel-mask = <0xfa>;
|
|
iommus = <&apps_smmu 0x6d6 0x0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
qupv3_id_1: geniqup@ac0000 {
|
|
compatible = "qcom,geni-se-qup";
|
|
reg = <0 0x00ac0000 0 0x6000>;
|
|
clock-names = "m-ahb", "s-ahb";
|
|
clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
|
|
iommus = <&apps_smmu 0x6c3 0x0>;
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
status = "disabled";
|
|
|
|
i2c8: i2c@a80000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0 0x00a80000 0 0x4000>;
|
|
clock-names = "se";
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&qup_i2c8_default>;
|
|
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
power-domains = <&rpmhpd SDM670_CX>;
|
|
dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
|
|
<&gpi_dma1 1 0 QCOM_GPI_I2C>;
|
|
dma-names = "tx", "rx";
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c9: i2c@a84000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0 0x00a84000 0 0x4000>;
|
|
clock-names = "se";
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&qup_i2c9_default>;
|
|
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
power-domains = <&rpmhpd SDM670_CX>;
|
|
dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
|
|
<&gpi_dma1 1 1 QCOM_GPI_I2C>;
|
|
dma-names = "tx", "rx";
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c10: i2c@a88000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0 0x00a88000 0 0x4000>;
|
|
clock-names = "se";
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&qup_i2c10_default>;
|
|
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
power-domains = <&rpmhpd SDM670_CX>;
|
|
dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
|
|
<&gpi_dma1 1 2 QCOM_GPI_I2C>;
|
|
dma-names = "tx", "rx";
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c11: i2c@a8c000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0 0x00a8c000 0 0x4000>;
|
|
clock-names = "se";
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&qup_i2c11_default>;
|
|
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
power-domains = <&rpmhpd SDM670_CX>;
|
|
dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
|
|
<&gpi_dma1 1 3 QCOM_GPI_I2C>;
|
|
dma-names = "tx", "rx";
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c12: i2c@a90000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0 0x00a90000 0 0x4000>;
|
|
clock-names = "se";
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&qup_i2c12_default>;
|
|
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
power-domains = <&rpmhpd SDM670_CX>;
|
|
dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
|
|
<&gpi_dma1 1 4 QCOM_GPI_I2C>;
|
|
dma-names = "tx", "rx";
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c13: i2c@a94000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0 0x00a94000 0 0x4000>;
|
|
clock-names = "se";
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&qup_i2c13_default>;
|
|
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
power-domains = <&rpmhpd SDM670_CX>;
|
|
dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
|
|
<&gpi_dma1 1 5 QCOM_GPI_I2C>;
|
|
dma-names = "tx", "rx";
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c14: i2c@a98000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0 0x00a98000 0 0x4000>;
|
|
clock-names = "se";
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&qup_i2c14_default>;
|
|
interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
power-domains = <&rpmhpd SDM670_CX>;
|
|
dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
|
|
<&gpi_dma1 1 6 QCOM_GPI_I2C>;
|
|
dma-names = "tx", "rx";
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c15: i2c@a9c000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0 0x00a9c000 0 0x4000>;
|
|
clock-names = "se";
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&qup_i2c15_default>;
|
|
interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
power-domains = <&rpmhpd SDM670_CX>;
|
|
dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>,
|
|
<&gpi_dma1 1 7 QCOM_GPI_I2C>;
|
|
dma-names = "tx", "rx";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
mem_noc: interconnect@1380000 {
|
|
compatible = "qcom,sdm670-mem-noc";
|
|
reg = <0 0x01380000 0 0x27200>;
|
|
#interconnect-cells = <2>;
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
};
|
|
|
|
dc_noc: interconnect@14e0000 {
|
|
compatible = "qcom,sdm670-dc-noc";
|
|
reg = <0 0x014e0000 0 0x400>;
|
|
#interconnect-cells = <2>;
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
};
|
|
|
|
config_noc: interconnect@1500000 {
|
|
compatible = "qcom,sdm670-config-noc";
|
|
reg = <0 0x01500000 0 0x5080>;
|
|
#interconnect-cells = <2>;
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
};
|
|
|
|
system_noc: interconnect@1620000 {
|
|
compatible = "qcom,sdm670-system-noc";
|
|
reg = <0 0x01620000 0 0x18080>;
|
|
#interconnect-cells = <2>;
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
};
|
|
|
|
aggre1_noc: interconnect@16e0000 {
|
|
compatible = "qcom,sdm670-aggre1-noc";
|
|
reg = <0 0x016e0000 0 0x15080>;
|
|
#interconnect-cells = <2>;
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
};
|
|
|
|
aggre2_noc: interconnect@1700000 {
|
|
compatible = "qcom,sdm670-aggre2-noc";
|
|
reg = <0 0x01700000 0 0x1f300>;
|
|
#interconnect-cells = <2>;
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
};
|
|
|
|
mmss_noc: interconnect@1740000 {
|
|
compatible = "qcom,sdm670-mmss-noc";
|
|
reg = <0 0x01740000 0 0x1c100>;
|
|
#interconnect-cells = <2>;
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
};
|
|
|
|
tlmm: pinctrl@3400000 {
|
|
compatible = "qcom,sdm670-tlmm";
|
|
reg = <0 0x03400000 0 0xc00000>;
|
|
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
gpio-ranges = <&tlmm 0 0 151>;
|
|
|
|
qup_i2c0_default: qup-i2c0-default-state {
|
|
pins = "gpio0", "gpio1";
|
|
function = "qup0";
|
|
};
|
|
|
|
qup_i2c1_default: qup-i2c1-default-state {
|
|
pins = "gpio17", "gpio18";
|
|
function = "qup1";
|
|
};
|
|
|
|
qup_i2c2_default: qup-i2c2-default-state {
|
|
pins = "gpio27", "gpio28";
|
|
function = "qup2";
|
|
};
|
|
|
|
qup_i2c3_default: qup-i2c3-default-state {
|
|
pins = "gpio41", "gpio42";
|
|
function = "qup3";
|
|
};
|
|
|
|
qup_i2c4_default: qup-i2c4-default-state {
|
|
pins = "gpio89", "gpio90";
|
|
function = "qup4";
|
|
};
|
|
|
|
qup_i2c5_default: qup-i2c5-default-state {
|
|
pins = "gpio85", "gpio86";
|
|
function = "qup5";
|
|
};
|
|
|
|
qup_i2c6_default: qup-i2c6-default-state {
|
|
pins = "gpio45", "gpio46";
|
|
function = "qup6";
|
|
};
|
|
|
|
qup_i2c7_default: qup-i2c7-default-state {
|
|
pins = "gpio93", "gpio94";
|
|
function = "qup7";
|
|
};
|
|
|
|
qup_i2c8_default: qup-i2c8-default-state {
|
|
pins = "gpio65", "gpio66";
|
|
function = "qup8";
|
|
};
|
|
|
|
qup_i2c9_default: qup-i2c9-default-state {
|
|
pins = "gpio6", "gpio7";
|
|
function = "qup9";
|
|
};
|
|
|
|
qup_i2c10_default: qup-i2c10-default-state {
|
|
pins = "gpio55", "gpio56";
|
|
function = "qup10";
|
|
};
|
|
|
|
qup_i2c11_default: qup-i2c11-default-state {
|
|
pins = "gpio31", "gpio32";
|
|
function = "qup11";
|
|
};
|
|
|
|
qup_i2c12_default: qup-i2c12-default-state {
|
|
pins = "gpio49", "gpio50";
|
|
function = "qup12";
|
|
};
|
|
|
|
qup_i2c13_default: qup-i2c13-default-state {
|
|
pins = "gpio105", "gpio106";
|
|
function = "qup13";
|
|
};
|
|
|
|
qup_i2c14_default: qup-i2c14-default-state {
|
|
pins = "gpio33", "gpio34";
|
|
function = "qup14";
|
|
};
|
|
|
|
qup_i2c15_default: qup-i2c15-default-state {
|
|
pins = "gpio81", "gpio82";
|
|
function = "qup15";
|
|
};
|
|
|
|
sdc1_state_on: sdc1-on-state {
|
|
clk-pins {
|
|
pins = "sdc1_clk";
|
|
bias-disable;
|
|
drive-strength = <16>;
|
|
};
|
|
|
|
cmd-pins {
|
|
pins = "sdc1_cmd";
|
|
bias-pull-up;
|
|
drive-strength = <10>;
|
|
};
|
|
|
|
data-pins {
|
|
pins = "sdc1_data";
|
|
bias-pull-up;
|
|
drive-strength = <10>;
|
|
};
|
|
|
|
rclk-pins {
|
|
pins = "sdc1_rclk";
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
|
|
sdc1_state_off: sdc1-off-state {
|
|
clk-pins {
|
|
pins = "sdc1_clk";
|
|
bias-disable;
|
|
drive-strength = <2>;
|
|
};
|
|
|
|
cmd-pins {
|
|
pins = "sdc1_cmd";
|
|
bias-pull-up;
|
|
drive-strength = <2>;
|
|
};
|
|
|
|
data-pins {
|
|
pins = "sdc1_data";
|
|
bias-pull-up;
|
|
drive-strength = <2>;
|
|
};
|
|
|
|
rclk-pins {
|
|
pins = "sdc1_rclk";
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
};
|
|
|
|
usb_1_hsphy: phy@88e2000 {
|
|
compatible = "qcom,sdm670-qusb2-phy", "qcom,qusb2-v2-phy";
|
|
reg = <0 0x088e2000 0 0x400>;
|
|
#phy-cells = <0>;
|
|
|
|
clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
|
|
<&rpmhcc RPMH_CXO_CLK>;
|
|
clock-names = "cfg_ahb", "ref";
|
|
|
|
resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
|
|
|
|
nvmem-cells = <&qusb2_hstx_trim>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
usb_1: usb@a6f8800 {
|
|
compatible = "qcom,sdm670-dwc3", "qcom,dwc3";
|
|
reg = <0 0x0a6f8800 0 0x400>;
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
dma-ranges;
|
|
|
|
clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
|
|
<&gcc GCC_USB30_PRIM_MASTER_CLK>,
|
|
<&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
|
|
<&gcc GCC_USB30_PRIM_SLEEP_CLK>,
|
|
<&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
|
|
clock-names = "cfg_noc",
|
|
"core",
|
|
"iface",
|
|
"sleep",
|
|
"mock_utmi";
|
|
|
|
assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
|
|
<&gcc GCC_USB30_PRIM_MASTER_CLK>;
|
|
assigned-clock-rates = <19200000>, <150000000>;
|
|
|
|
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "hs_phy_irq", "ss_phy_irq",
|
|
"dm_hs_phy_irq", "dp_hs_phy_irq";
|
|
|
|
power-domains = <&gcc USB30_PRIM_GDSC>;
|
|
|
|
resets = <&gcc GCC_USB30_PRIM_BCR>;
|
|
|
|
status = "disabled";
|
|
|
|
usb_1_dwc3: usb@a600000 {
|
|
compatible = "snps,dwc3";
|
|
reg = <0 0x0a600000 0 0xcd00>;
|
|
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
|
|
iommus = <&apps_smmu 0x740 0>;
|
|
snps,dis_u2_susphy_quirk;
|
|
snps,dis_enblslpm_quirk;
|
|
phys = <&usb_1_hsphy>;
|
|
phy-names = "usb2-phy";
|
|
};
|
|
};
|
|
|
|
spmi_bus: spmi@c440000 {
|
|
compatible = "qcom,spmi-pmic-arb";
|
|
reg = <0 0x0c440000 0 0x1100>,
|
|
<0 0x0c600000 0 0x2000000>,
|
|
<0 0x0e600000 0 0x100000>,
|
|
<0 0x0e700000 0 0xa0000>,
|
|
<0 0x0c40a000 0 0x26000>;
|
|
reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
|
|
interrupt-names = "periph_irq";
|
|
interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
|
|
qcom,ee = <0>;
|
|
qcom,channel = <0>;
|
|
#address-cells = <2>;
|
|
#size-cells = <0>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <4>;
|
|
};
|
|
|
|
apps_smmu: iommu@15000000 {
|
|
compatible = "qcom,sdm670-smmu-500", "qcom,smmu-500", "arm,mmu-500";
|
|
reg = <0 0x15000000 0 0x80000>;
|
|
#iommu-cells = <2>;
|
|
#global-interrupts = <1>;
|
|
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
gladiator_noc: interconnect@17900000 {
|
|
compatible = "qcom,sdm670-gladiator-noc";
|
|
reg = <0 0x17900000 0 0xd080>;
|
|
#interconnect-cells = <2>;
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
};
|
|
|
|
apps_rsc: rsc@179c0000 {
|
|
compatible = "qcom,rpmh-rsc";
|
|
reg = <0 0x179c0000 0 0x10000>,
|
|
<0 0x179d0000 0 0x10000>,
|
|
<0 0x179e0000 0 0x10000>;
|
|
reg-names = "drv-0", "drv-1", "drv-2";
|
|
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
|
|
label = "apps_rsc";
|
|
qcom,tcs-offset = <0xd00>;
|
|
qcom,drv-id = <2>;
|
|
qcom,tcs-config = <ACTIVE_TCS 2>,
|
|
<SLEEP_TCS 3>,
|
|
<WAKE_TCS 3>,
|
|
<CONTROL_TCS 1>;
|
|
|
|
apps_bcm_voter: bcm-voter {
|
|
compatible = "qcom,bcm-voter";
|
|
};
|
|
|
|
rpmhcc: clock-controller {
|
|
compatible = "qcom,sdm670-rpmh-clk";
|
|
#clock-cells = <1>;
|
|
clock-names = "xo";
|
|
clocks = <&xo_board>;
|
|
};
|
|
|
|
rpmhpd: power-controller {
|
|
compatible = "qcom,sdm670-rpmhpd";
|
|
#power-domain-cells = <1>;
|
|
operating-points-v2 = <&rpmhpd_opp_table>;
|
|
|
|
rpmhpd_opp_table: opp-table {
|
|
compatible = "operating-points-v2";
|
|
|
|
rpmhpd_opp_ret: opp1 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
|
|
};
|
|
|
|
rpmhpd_opp_min_svs: opp2 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
|
|
};
|
|
|
|
rpmhpd_opp_low_svs: opp3 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
|
};
|
|
|
|
rpmhpd_opp_svs: opp4 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
|
|
};
|
|
|
|
rpmhpd_opp_svs_l1: opp5 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
|
};
|
|
|
|
rpmhpd_opp_nom: opp6 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
|
|
};
|
|
|
|
rpmhpd_opp_nom_l1: opp7 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
|
|
};
|
|
|
|
rpmhpd_opp_nom_l2: opp8 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
|
|
};
|
|
|
|
rpmhpd_opp_turbo: opp9 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
|
|
};
|
|
|
|
rpmhpd_opp_turbo_l1: opp10 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
intc: interrupt-controller@17a00000 {
|
|
compatible = "arm,gic-v3";
|
|
reg = <0 0x17a00000 0 0x10000>, /* GICD */
|
|
<0 0x17a60000 0 0x100000>; /* GICR * 8 */
|
|
interrupt-controller;
|
|
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
|
#interrupt-cells = <3>;
|
|
};
|
|
};
|
|
};
|