304 lines
9.7 KiB
Plaintext
304 lines
9.7 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
|
/*
|
|
* Device Tree Source for the RZ/V2M SoC
|
|
*
|
|
* Copyright (C) 2022 Renesas Electronics Corp.
|
|
*/
|
|
|
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
|
#include <dt-bindings/clock/r9a09g011-cpg.h>
|
|
|
|
/ {
|
|
compatible = "renesas,r9a09g011";
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
|
|
/* clock can be either from exclk or crystal oscillator (XIN/XOUT) */
|
|
extal_clk: extal {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
/* This value must be overridden by the board */
|
|
clock-frequency = <0>;
|
|
};
|
|
|
|
cpus {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
cpu-map {
|
|
cluster0 {
|
|
core0 {
|
|
cpu = <&cpu0>;
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu0: cpu@0 {
|
|
compatible = "arm,cortex-a53";
|
|
reg = <0>;
|
|
device_type = "cpu";
|
|
next-level-cache = <&L2_CA53>;
|
|
clocks = <&cpg CPG_MOD R9A09G011_CA53_CLK>;
|
|
};
|
|
|
|
L2_CA53: cache-controller-0 {
|
|
compatible = "cache";
|
|
cache-unified;
|
|
cache-level = <2>;
|
|
};
|
|
};
|
|
|
|
soc: soc {
|
|
compatible = "simple-bus";
|
|
interrupt-parent = <&gic>;
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
|
|
gic: interrupt-controller@82010000 {
|
|
compatible = "arm,gic-400";
|
|
#interrupt-cells = <3>;
|
|
#address-cells = <0>;
|
|
interrupt-controller;
|
|
reg = <0x0 0x82010000 0 0x1000>,
|
|
<0x0 0x82020000 0 0x20000>,
|
|
<0x0 0x82040000 0 0x20000>,
|
|
<0x0 0x82060000 0 0x20000>;
|
|
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
|
|
clocks = <&cpg CPG_MOD R9A09G011_GIC_CLK>;
|
|
clock-names = "clk";
|
|
};
|
|
|
|
sdhi0: mmc@85000000 {
|
|
compatible = "renesas,sdhi-r9a09g011",
|
|
"renesas,rcar-gen3-sdhi";
|
|
reg = <0x0 0x85000000 0 0x2000>;
|
|
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD R9A09G011_SDI0_IMCLK>,
|
|
<&cpg CPG_MOD R9A09G011_SDI0_CLK_HS>,
|
|
<&cpg CPG_MOD R9A09G011_SDI0_IMCLK2>,
|
|
<&cpg CPG_MOD R9A09G011_SDI0_ACLK>;
|
|
clock-names = "core", "clkh", "cd", "aclk";
|
|
resets = <&cpg R9A09G011_SDI0_IXRST>;
|
|
power-domains = <&cpg>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sdhi1: mmc@85010000 {
|
|
compatible = "renesas,sdhi-r9a09g011",
|
|
"renesas,rcar-gen3-sdhi";
|
|
reg = <0x0 0x85010000 0 0x2000>;
|
|
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD R9A09G011_SDI1_IMCLK>,
|
|
<&cpg CPG_MOD R9A09G011_SDI1_CLK_HS>,
|
|
<&cpg CPG_MOD R9A09G011_SDI1_IMCLK2>,
|
|
<&cpg CPG_MOD R9A09G011_SDI1_ACLK>;
|
|
clock-names = "core", "clkh", "cd", "aclk";
|
|
resets = <&cpg R9A09G011_SDI1_IXRST>;
|
|
power-domains = <&cpg>;
|
|
status = "disabled";
|
|
};
|
|
|
|
emmc: mmc@85020000 {
|
|
compatible = "renesas,sdhi-r9a09g011",
|
|
"renesas,rcar-gen3-sdhi";
|
|
reg = <0x0 0x85020000 0 0x2000>;
|
|
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD R9A09G011_EMM_IMCLK>,
|
|
<&cpg CPG_MOD R9A09G011_EMM_CLK_HS>,
|
|
<&cpg CPG_MOD R9A09G011_EMM_IMCLK2>,
|
|
<&cpg CPG_MOD R9A09G011_EMM_ACLK>;
|
|
clock-names = "core", "clkh", "cd", "aclk";
|
|
resets = <&cpg R9A09G011_EMM_IXRST>;
|
|
power-domains = <&cpg>;
|
|
status = "disabled";
|
|
};
|
|
|
|
avb: ethernet@a3300000 {
|
|
compatible = "renesas,etheravb-r9a09g011","renesas,etheravb-rzv2m";
|
|
reg = <0 0xa3300000 0 0x800>;
|
|
interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, /* ch0: Rx0 BE */
|
|
<GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, /* ch1: Rx1 NC */
|
|
<GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, /* ch18: Tx0 BE */
|
|
<GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, /* ch19: Tx1 NC */
|
|
<GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, /* DiA */
|
|
<GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, /* DiB */
|
|
<GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, /* Line1_A */
|
|
<GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, /* Line1_B */
|
|
<GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, /* Line2_A */
|
|
<GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, /* Line2_B */
|
|
<GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>; /* Line3 MAC */
|
|
interrupt-names = "ch0", "ch1", "ch2", "ch3",
|
|
"ch4", "ch5", "ch6", "ch7",
|
|
"ch8", "ch9", "ch10", "ch11",
|
|
"ch12", "ch13", "ch14", "ch15",
|
|
"ch16", "ch17", "ch18", "ch19",
|
|
"ch20", "ch21", "dia", "dib",
|
|
"err_a", "err_b", "mgmt_a", "mgmt_b",
|
|
"line3";
|
|
clocks = <&cpg CPG_MOD R9A09G011_ETH0_CLK_AXI>,
|
|
<&cpg CPG_MOD R9A09G011_ETH0_CLK_CHI>,
|
|
<&cpg CPG_MOD R9A09G011_ETH0_GPTP_EXT>;
|
|
clock-names = "axi", "chi", "gptp";
|
|
resets = <&cpg R9A09G011_ETH0_RST_HW_N>;
|
|
power-domains = <&cpg>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
cpg: clock-controller@a3500000 {
|
|
compatible = "renesas,r9a09g011-cpg";
|
|
reg = <0 0xa3500000 0 0x1000>;
|
|
clocks = <&extal_clk>;
|
|
clock-names = "extal";
|
|
#clock-cells = <2>;
|
|
#reset-cells = <1>;
|
|
#power-domain-cells = <0>;
|
|
};
|
|
|
|
pwc: pwc@a3700000 {
|
|
compatible = "renesas,r9a09g011-pwc", "renesas,rzv2m-pwc";
|
|
reg = <0 0xa3700000 0 0x800>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sys: system-controller@a3f03000 {
|
|
compatible = "renesas,r9a09g011-sys";
|
|
reg = <0 0xa3f03000 0 0x400>;
|
|
};
|
|
|
|
i2c0: i2c@a4030000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "renesas,r9a09g011-i2c", "renesas,rzv2m-i2c";
|
|
reg = <0 0xa4030000 0 0x80>;
|
|
interrupts = <GIC_SPI 232 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 236 IRQ_TYPE_EDGE_RISING>;
|
|
interrupt-names = "tia", "tis";
|
|
clocks = <&cpg CPG_MOD R9A09G011_IIC_PCLK0>;
|
|
resets = <&cpg R9A09G011_IIC_GPA_PRESETN>;
|
|
power-domains = <&cpg>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c2: i2c@a4030100 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "renesas,r9a09g011-i2c", "renesas,rzv2m-i2c";
|
|
reg = <0 0xa4030100 0 0x80>;
|
|
interrupts = <GIC_SPI 234 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 238 IRQ_TYPE_EDGE_RISING>;
|
|
interrupt-names = "tia", "tis";
|
|
clocks = <&cpg CPG_MOD R9A09G011_IIC_PCLK1>;
|
|
resets = <&cpg R9A09G011_IIC_GPB_PRESETN>;
|
|
power-domains = <&cpg>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart0: serial@a4040000 {
|
|
compatible = "renesas,r9a09g011-uart", "renesas,em-uart";
|
|
reg = <0 0xa4040000 0 0x80>;
|
|
interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD R9A09G011_URT0_CLK>,
|
|
<&cpg CPG_MOD R9A09G011_URT_PCLK>;
|
|
clock-names = "sclk", "pclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
wdt0: watchdog@a4050000 {
|
|
compatible = "renesas,r9a09g011-wdt",
|
|
"renesas,rzv2m-wdt";
|
|
reg = <0 0xa4050000 0 0x80>;
|
|
clocks = <&cpg CPG_MOD R9A09G011_WDT0_PCLK>,
|
|
<&cpg CPG_MOD R9A09G011_WDT0_CLK>;
|
|
clock-names = "pclk", "oscclk";
|
|
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
|
|
resets = <&cpg R9A09G011_WDT0_PRESETN>;
|
|
power-domains = <&cpg>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pinctrl: pinctrl@b6250000 {
|
|
compatible = "renesas,r9a09g011-pinctrl";
|
|
reg = <0 0xb6250000 0 0x800>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
gpio-ranges = <&pinctrl 0 0 352>;
|
|
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD R9A09G011_PFC_PCLK>;
|
|
power-domains = <&cpg>;
|
|
resets = <&cpg R9A09G011_PFC_PRESETN>;
|
|
};
|
|
};
|
|
|
|
timer {
|
|
compatible = "arm,armv8-timer";
|
|
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
|
|
};
|
|
};
|