232 lines
5.8 KiB
Plaintext
232 lines
5.8 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2021 PHYTEC America, LLC - https://www.phytec.com
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* Author: Matt McKee <mmckee@phytec.com>
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*
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* Copyright (C) 2022 PHYTEC Messtechnik GmbH
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* Author: Wadim Egorov <w.egorov@phytec.de>
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*
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* Product homepage:
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* https://www.phytec.com/product/phycore-am64x
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/leds/common.h>
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#include <dt-bindings/net/ti-dp83867.h>
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/ {
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model = "PHYTEC phyCORE-AM64x";
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compatible = "phytec,am64-phycore-som", "ti,am642";
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aliases {
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ethernet0 = &cpsw_port1;
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mmc0 = &sdhci0;
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rtc0 = &i2c_som_rtc;
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};
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memory@80000000 {
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device_type = "memory";
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reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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secure_ddr: optee@9e800000 {
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reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
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alignment = <0x1000>;
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no-map;
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};
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};
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leds {
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compatible = "gpio-leds";
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pinctrl-names = "default";
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pinctrl-0 = <&leds_pins_default>;
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led-0 {
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color = <LED_COLOR_ID_GREEN>;
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gpios = <&main_gpio0 12 GPIO_ACTIVE_HIGH>;
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linux,default-trigger = "heartbeat";
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function = LED_FUNCTION_HEARTBEAT;
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};
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};
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vcc_5v0_som: regulator-vcc-5v0-som {
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/* VIN / VCC_5V0_SOM */
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compatible = "regulator-fixed";
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regulator-name = "VCC_5V0_SOM";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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regulator-always-on;
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regulator-boot-on;
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};
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};
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&main_pmx0 {
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cpsw_mdio_pins_default: cpsw-mdio-pins-default {
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pinctrl-single,pins = <
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AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */
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AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */
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AM64X_IOPAD(0x0100, PIN_OUTPUT, 7) /* (V7) PRG1_PRU0_GPO18.GPIO0_63 */
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>;
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};
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cpsw_rgmii1_pins_default: cpsw-rgmii1-pins-default {
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pinctrl-single,pins = <
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AM64X_IOPAD(0x0184, PIN_INPUT, 4) /* (W6) PRG0_PRU0_GPO9.RGMII1_RX_CTL */
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AM64X_IOPAD(0x0188, PIN_INPUT, 4) /* (AA5) PRG0_PRU0_GPO10.RGMII1_RXC */
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AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* (U15) PRG1_PRU0_GPO9.RGMII1_TX_CTL */
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AM64X_IOPAD(0x00e0, PIN_OUTPUT, 4) /* (U14) PRG1_PRU0_GPO10.RGMII1_TXC */
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AM64X_IOPAD(0x01cc, PIN_INPUT, 4) /* (W5) PRG0_PRU1_GPO7.RGMII1_RD0 */
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AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* (V15) PRG1_PRU1_GPO7.RGMII1_TD0 */
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AM64X_IOPAD(0x01d4, PIN_INPUT, 4) /* (Y5) PRG0_PRU1_GPO9.RGMII1_RD1 */
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AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* (V14) PRG1_PRU1_GPO9.RGMII1_TD1 */
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AM64X_IOPAD(0x01d8, PIN_INPUT, 4) /* (V6) PRG0_PRU1_GPO10.RGMII1_RD2 */
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AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* (W14) PRG1_PRU1_GPO10.RGMII1_TD2 */
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AM64X_IOPAD(0x01f4, PIN_INPUT, 4) /* (V5) PRG0_PRU1_GPO17.RGMII1_RD3 */
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AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */
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AM64X_IOPAD(0x0154, PIN_INPUT, 7) /* (V12) PRG1_PRU1_GPO19.GPIO0_84 */
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>;
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};
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eeprom_wp_pins_default: eeprom-wp-pins-default {
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pinctrl-single,pins = <
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AM64X_IOPAD(0x0208, PIN_OUTPUT, 7) /* (D12) SPI0_CS0.GPIO1_42 */
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>;
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};
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leds_pins_default: leds-pins-default {
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pinctrl-single,pins = <
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AM64X_IOPAD(0x0030, PIN_OUTPUT, 7) /* (L18) OSPI0_CSn1.GPIO0_12 */
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>;
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};
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main_i2c0_pins_default: main-i2c0-pins-default {
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pinctrl-single,pins = <
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AM64X_IOPAD(0x0260, PIN_INPUT, 0) /* (A18) I2C0_SCL */
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AM64X_IOPAD(0x0264, PIN_INPUT, 0) /* (B18) I2C0_SDA */
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>;
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};
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ospi0_pins_default: ospi0-pins-default {
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pinctrl-single,pins = <
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AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) /* (N20) OSPI0_CLK */
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AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */
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AM64X_IOPAD(0x000c, PIN_INPUT, 0) /* (M19) OSPI0_D0 */
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AM64X_IOPAD(0x0010, PIN_INPUT, 0) /* (M18) OSPI0_D1 */
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AM64X_IOPAD(0x0014, PIN_INPUT, 0) /* (M20) OSPI0_D2 */
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AM64X_IOPAD(0x0018, PIN_INPUT, 0) /* (M21) OSPI0_D3 */
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AM64X_IOPAD(0x001c, PIN_INPUT, 0) /* (P21) OSPI0_D4 */
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AM64X_IOPAD(0x0020, PIN_INPUT, 0) /* (P20) OSPI0_D5 */
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AM64X_IOPAD(0x0024, PIN_INPUT, 0) /* (N18) OSPI0_D6 */
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AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */
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AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (L19) OSPI0_CSn0 */
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>;
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};
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};
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&cpsw3g {
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pinctrl-names = "default";
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pinctrl-0 = <&cpsw_rgmii1_pins_default>;
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};
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&cpsw3g_mdio {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&cpsw_mdio_pins_default>;
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cpsw3g_phy1: ethernet-phy@1 {
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compatible = "ethernet-phy-id2000.a231", "ethernet-phy-ieee802.3-c22";
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reg = <1>;
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interrupt-parent = <&main_gpio0>;
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interrupts = <84 IRQ_TYPE_EDGE_FALLING>;
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ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
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ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
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reset-gpios = <&main_gpio0 63 GPIO_ACTIVE_LOW>;
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reset-assert-us = <1000>;
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reset-deassert-us = <1000>;
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};
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};
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&cpsw_port1 {
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phy-mode = "rgmii-rxid";
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phy-handle = <&cpsw3g_phy1>;
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};
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&cpsw_port2 {
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status = "disabled";
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};
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&mailbox0_cluster2 {
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status = "disabled";
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};
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&mailbox0_cluster3 {
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status = "disabled";
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};
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&mailbox0_cluster4 {
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status = "disabled";
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};
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&mailbox0_cluster5 {
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status = "disabled";
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};
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&mailbox0_cluster6 {
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status = "disabled";
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};
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&mailbox0_cluster7 {
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status = "disabled";
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};
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&main_i2c0 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&main_i2c0_pins_default>;
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clock-frequency = <400000>;
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eeprom@50 {
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compatible = "atmel,24c32";
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pinctrl-names = "default";
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pinctrl-0 = <&eeprom_wp_pins_default>;
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pagesize = <32>;
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reg = <0x50>;
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};
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i2c_som_rtc: rtc@52 {
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compatible = "microcrystal,rv3028";
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reg = <0x52>;
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};
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};
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&ospi0 {
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pinctrl-names = "default";
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pinctrl-0 = <&ospi0_pins_default>;
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flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0x0>;
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spi-tx-bus-width = <8>;
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spi-rx-bus-width = <8>;
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spi-max-frequency = <25000000>;
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cdns,tshsl-ns = <60>;
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cdns,tsd2d-ns = <60>;
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cdns,tchsh-ns = <60>;
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cdns,tslch-ns = <60>;
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cdns,read-delay = <0>;
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};
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};
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&sdhci0 {
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bus-width = <8>;
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non-removable;
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ti,driver-strength-ohm = <50>;
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disable-wp;
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keep-power-in-suspend;
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};
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