213 lines
5.2 KiB
C
213 lines
5.2 KiB
C
/*
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* intc-2.c
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*
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* General interrupt controller code for the many ColdFire cores that use
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* interrupt controllers with 63 interrupt sources, organized as 56 fully-
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* programmable + 7 fixed-level interrupt sources. This includes the 523x
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* family, the 5270, 5271, 5274, 5275, and the 528x family which have two such
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* controllers, and the 547x and 548x families which have only one of them.
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*
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* The external 7 fixed interrupts are part of the Edge Port unit of these
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* ColdFire parts. They can be configured as level or edge triggered.
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*
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* (C) Copyright 2009-2011, Greg Ungerer <gerg@snapgear.com>
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file COPYING in the main directory of this archive
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* for more details.
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*/
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#include <linux/types.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <asm/coldfire.h>
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#include <asm/mcfsim.h>
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#include <asm/traps.h>
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/*
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* Bit definitions for the ICR family of registers.
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*/
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#define MCFSIM_ICR_LEVEL(l) ((l)<<3) /* Level l intr */
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#define MCFSIM_ICR_PRI(p) (p) /* Priority p intr */
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/*
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* The EDGE Port interrupts are the fixed 7 external interrupts.
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* They need some special treatment, for example they need to be acked.
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*/
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#define EINT0 64 /* Is not actually used, but spot reserved for it */
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#define EINT1 65 /* EDGE Port interrupt 1 */
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#define EINT7 71 /* EDGE Port interrupt 7 */
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#ifdef MCFICM_INTC1
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#define NR_VECS 128
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#else
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#define NR_VECS 64
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#endif
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static void intc_irq_mask(struct irq_data *d)
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{
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unsigned int irq = d->irq - MCFINT_VECBASE;
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unsigned long imraddr;
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u32 val, imrbit;
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#ifdef MCFICM_INTC1
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imraddr = (irq & 0x40) ? MCFICM_INTC1 : MCFICM_INTC0;
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#else
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imraddr = MCFICM_INTC0;
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#endif
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imraddr += (irq & 0x20) ? MCFINTC_IMRH : MCFINTC_IMRL;
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imrbit = 0x1 << (irq & 0x1f);
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val = __raw_readl(imraddr);
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__raw_writel(val | imrbit, imraddr);
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}
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static void intc_irq_unmask(struct irq_data *d)
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{
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unsigned int irq = d->irq - MCFINT_VECBASE;
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unsigned long imraddr;
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u32 val, imrbit;
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#ifdef MCFICM_INTC1
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imraddr = (irq & 0x40) ? MCFICM_INTC1 : MCFICM_INTC0;
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#else
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imraddr = MCFICM_INTC0;
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#endif
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imraddr += ((irq & 0x20) ? MCFINTC_IMRH : MCFINTC_IMRL);
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imrbit = 0x1 << (irq & 0x1f);
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/* Don't set the "maskall" bit! */
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if ((irq & 0x20) == 0)
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imrbit |= 0x1;
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val = __raw_readl(imraddr);
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__raw_writel(val & ~imrbit, imraddr);
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}
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/*
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* Only the external (or EDGE Port) interrupts need to be acknowledged
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* here, as part of the IRQ handler. They only really need to be ack'ed
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* if they are in edge triggered mode, but there is no harm in doing it
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* for all types.
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*/
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static void intc_irq_ack(struct irq_data *d)
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{
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unsigned int irq = d->irq;
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__raw_writeb(0x1 << (irq - EINT0), MCFEPORT_EPFR);
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}
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/*
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* Each vector needs a unique priority and level associated with it.
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* We don't really care so much what they are, we don't rely on the
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* traditional priority interrupt scheme of the m68k/ColdFire. This
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* only needs to be set once for an interrupt, and we will never change
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* these values once we have set them.
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*/
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static u8 intc_intpri = MCFSIM_ICR_LEVEL(6) | MCFSIM_ICR_PRI(6);
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static unsigned int intc_irq_startup(struct irq_data *d)
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{
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unsigned int irq = d->irq - MCFINT_VECBASE;
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unsigned long icraddr;
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#ifdef MCFICM_INTC1
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icraddr = (irq & 0x40) ? MCFICM_INTC1 : MCFICM_INTC0;
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#else
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icraddr = MCFICM_INTC0;
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#endif
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icraddr += MCFINTC_ICR0 + (irq & 0x3f);
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if (__raw_readb(icraddr) == 0)
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__raw_writeb(intc_intpri--, icraddr);
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irq = d->irq;
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if ((irq >= EINT1) && (irq <= EINT7)) {
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u8 v;
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irq -= EINT0;
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/* Set EPORT line as input */
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v = __raw_readb(MCFEPORT_EPDDR);
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__raw_writeb(v & ~(0x1 << irq), MCFEPORT_EPDDR);
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/* Set EPORT line as interrupt source */
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v = __raw_readb(MCFEPORT_EPIER);
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__raw_writeb(v | (0x1 << irq), MCFEPORT_EPIER);
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}
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intc_irq_unmask(d);
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return 0;
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}
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static int intc_irq_set_type(struct irq_data *d, unsigned int type)
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{
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unsigned int irq = d->irq;
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u16 pa, tb;
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switch (type) {
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case IRQ_TYPE_EDGE_RISING:
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tb = 0x1;
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break;
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case IRQ_TYPE_EDGE_FALLING:
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tb = 0x2;
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break;
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case IRQ_TYPE_EDGE_BOTH:
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tb = 0x3;
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break;
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default:
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/* Level triggered */
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tb = 0;
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break;
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}
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if (tb)
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irq_set_handler(irq, handle_edge_irq);
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irq -= EINT0;
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pa = __raw_readw(MCFEPORT_EPPAR);
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pa = (pa & ~(0x3 << (irq * 2))) | (tb << (irq * 2));
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__raw_writew(pa, MCFEPORT_EPPAR);
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return 0;
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}
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static struct irq_chip intc_irq_chip = {
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.name = "CF-INTC",
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.irq_startup = intc_irq_startup,
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.irq_mask = intc_irq_mask,
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.irq_unmask = intc_irq_unmask,
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};
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static struct irq_chip intc_irq_chip_edge_port = {
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.name = "CF-INTC-EP",
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.irq_startup = intc_irq_startup,
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.irq_mask = intc_irq_mask,
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.irq_unmask = intc_irq_unmask,
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.irq_ack = intc_irq_ack,
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.irq_set_type = intc_irq_set_type,
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};
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void __init init_IRQ(void)
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{
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int irq;
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/* Mask all interrupt sources */
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__raw_writel(0x1, MCFICM_INTC0 + MCFINTC_IMRL);
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#ifdef MCFICM_INTC1
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__raw_writel(0x1, MCFICM_INTC1 + MCFINTC_IMRL);
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#endif
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for (irq = MCFINT_VECBASE; (irq < MCFINT_VECBASE + NR_VECS); irq++) {
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if ((irq >= EINT1) && (irq <=EINT7))
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irq_set_chip(irq, &intc_irq_chip_edge_port);
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else
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irq_set_chip(irq, &intc_irq_chip);
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irq_set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH);
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irq_set_handler(irq, handle_level_irq);
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}
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}
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