155 lines
3.6 KiB
C
155 lines
3.6 KiB
C
// SPDX-License-Identifier: GPL-2.0
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/sched/debug.h>
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#include <linux/types.h>
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#include <linux/ioport.h>
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#include <asm/hwtest.h>
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#include <asm/irq.h>
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#include <asm/irq_regs.h>
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#include <asm/processor.h>
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#include <asm/virt.h>
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#define GFPIC_REG_IRQ_PENDING 0x04
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#define GFPIC_REG_IRQ_DISABLE_ALL 0x08
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#define GFPIC_REG_IRQ_DISABLE 0x0c
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#define GFPIC_REG_IRQ_ENABLE 0x10
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static struct resource picres[6];
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static const char *picname[6] = {
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"goldfish_pic.0",
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"goldfish_pic.1",
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"goldfish_pic.2",
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"goldfish_pic.3",
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"goldfish_pic.4",
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"goldfish_pic.5"
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};
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/*
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* 6 goldfish-pic for CPU IRQ #1 to IRQ #6
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* CPU IRQ #1 -> PIC #1
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* IRQ #1 to IRQ #31 -> unused
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* IRQ #32 -> goldfish-tty
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* CPU IRQ #2 -> PIC #2
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* IRQ #1 to IRQ #32 -> virtio-mmio from 1 to 32
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* CPU IRQ #3 -> PIC #3
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* IRQ #1 to IRQ #32 -> virtio-mmio from 33 to 64
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* CPU IRQ #4 -> PIC #4
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* IRQ #1 to IRQ #32 -> virtio-mmio from 65 to 96
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* CPU IRQ #5 -> PIC #5
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* IRQ #1 to IRQ #32 -> virtio-mmio from 97 to 128
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* CPU IRQ #6 -> PIC #6
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* IRQ #1 -> goldfish-timer
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* IRQ #2 -> goldfish-rtc
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* IRQ #3 to IRQ #32 -> unused
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* CPU IRQ #7 -> NMI
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*/
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static u32 gfpic_read(int pic, int reg)
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{
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void __iomem *base = (void __iomem *)(virt_bi_data.pic.mmio +
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pic * 0x1000);
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return ioread32be(base + reg);
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}
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static void gfpic_write(u32 value, int pic, int reg)
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{
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void __iomem *base = (void __iomem *)(virt_bi_data.pic.mmio +
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pic * 0x1000);
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iowrite32be(value, base + reg);
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}
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#define GF_PIC(irq) ((irq - IRQ_USER) / 32)
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#define GF_IRQ(irq) ((irq - IRQ_USER) % 32)
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static void virt_irq_enable(struct irq_data *data)
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{
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gfpic_write(BIT(GF_IRQ(data->irq)), GF_PIC(data->irq),
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GFPIC_REG_IRQ_ENABLE);
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}
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static void virt_irq_disable(struct irq_data *data)
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{
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gfpic_write(BIT(GF_IRQ(data->irq)), GF_PIC(data->irq),
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GFPIC_REG_IRQ_DISABLE);
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}
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static unsigned int virt_irq_startup(struct irq_data *data)
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{
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virt_irq_enable(data);
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return 0;
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}
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static irqreturn_t virt_nmi_handler(int irq, void *dev_id)
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{
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static int in_nmi;
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if (READ_ONCE(in_nmi))
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return IRQ_HANDLED;
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WRITE_ONCE(in_nmi, 1);
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pr_warn("Non-Maskable Interrupt\n");
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show_registers(get_irq_regs());
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WRITE_ONCE(in_nmi, 0);
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return IRQ_HANDLED;
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}
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static struct irq_chip virt_irq_chip = {
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.name = "virt",
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.irq_enable = virt_irq_enable,
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.irq_disable = virt_irq_disable,
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.irq_startup = virt_irq_startup,
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.irq_shutdown = virt_irq_disable,
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};
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static void goldfish_pic_irq(struct irq_desc *desc)
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{
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u32 irq_pending;
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unsigned int irq_num;
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unsigned int pic = desc->irq_data.irq - 1;
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irq_pending = gfpic_read(pic, GFPIC_REG_IRQ_PENDING);
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irq_num = IRQ_USER + pic * 32;
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do {
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if (irq_pending & 1)
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generic_handle_irq(irq_num);
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++irq_num;
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irq_pending >>= 1;
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} while (irq_pending);
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}
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void __init virt_init_IRQ(void)
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{
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unsigned int i;
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m68k_setup_irq_controller(&virt_irq_chip, handle_simple_irq, IRQ_USER,
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NUM_VIRT_SOURCES - IRQ_USER);
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for (i = 0; i < 6; i++) {
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picres[i] = (struct resource)
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DEFINE_RES_MEM_NAMED(virt_bi_data.pic.mmio + i * 0x1000,
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0x1000, picname[i]);
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if (request_resource(&iomem_resource, &picres[i])) {
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pr_err("Cannot allocate %s resource\n", picname[i]);
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return;
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}
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irq_set_chained_handler(virt_bi_data.pic.irq + i,
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goldfish_pic_irq);
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}
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if (request_irq(IRQ_AUTO_7, virt_nmi_handler, 0, "NMI",
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virt_nmi_handler))
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pr_err("Couldn't register NMI\n");
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}
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