137 lines
3.6 KiB
C
137 lines
3.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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*
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* Parts of this file are based on Ralink's 2.6.21 BSP
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*
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* Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
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* Copyright (C) 2013 John Crispin <john@phrozen.org>
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*/
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#ifndef _RT305X_REGS_H_
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#define _RT305X_REGS_H_
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extern enum ralink_soc_type ralink_soc;
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static inline int soc_is_rt3050(void)
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{
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return ralink_soc == RT305X_SOC_RT3050;
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}
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static inline int soc_is_rt3052(void)
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{
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return ralink_soc == RT305X_SOC_RT3052;
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}
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static inline int soc_is_rt305x(void)
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{
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return soc_is_rt3050() || soc_is_rt3052();
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}
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static inline int soc_is_rt3350(void)
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{
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return ralink_soc == RT305X_SOC_RT3350;
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}
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static inline int soc_is_rt3352(void)
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{
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return ralink_soc == RT305X_SOC_RT3352;
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}
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static inline int soc_is_rt5350(void)
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{
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return ralink_soc == RT305X_SOC_RT5350;
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}
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#define RT305X_SYSC_BASE 0x10000000
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#define SYSC_REG_CHIP_NAME0 0x00
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#define SYSC_REG_CHIP_NAME1 0x04
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#define SYSC_REG_CHIP_ID 0x0c
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#define SYSC_REG_SYSTEM_CONFIG 0x10
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#define RT3052_CHIP_NAME0 0x30335452
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#define RT3052_CHIP_NAME1 0x20203235
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#define RT3350_CHIP_NAME0 0x33335452
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#define RT3350_CHIP_NAME1 0x20203035
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#define RT3352_CHIP_NAME0 0x33335452
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#define RT3352_CHIP_NAME1 0x20203235
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#define RT5350_CHIP_NAME0 0x33355452
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#define RT5350_CHIP_NAME1 0x20203035
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#define CHIP_ID_ID_MASK 0xff
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#define CHIP_ID_ID_SHIFT 8
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#define CHIP_ID_REV_MASK 0xff
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#define RT305X_SYSCFG_CPUCLK_SHIFT 18
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#define RT305X_SYSCFG_CPUCLK_MASK 0x1
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#define RT305X_SYSCFG_CPUCLK_LOW 0x0
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#define RT305X_SYSCFG_CPUCLK_HIGH 0x1
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#define RT305X_SYSCFG_SRAM_CS0_MODE_SHIFT 2
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#define RT305X_SYSCFG_CPUCLK_MASK 0x1
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#define RT305X_SYSCFG_SRAM_CS0_MODE_WDT 0x1
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#define RT3352_SYSCFG0_CPUCLK_SHIFT 8
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#define RT3352_SYSCFG0_CPUCLK_MASK 0x1
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#define RT3352_SYSCFG0_CPUCLK_LOW 0x0
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#define RT3352_SYSCFG0_CPUCLK_HIGH 0x1
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#define RT5350_SYSCFG0_CPUCLK_SHIFT 8
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#define RT5350_SYSCFG0_CPUCLK_MASK 0x3
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#define RT5350_SYSCFG0_CPUCLK_360 0x0
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#define RT5350_SYSCFG0_CPUCLK_320 0x2
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#define RT5350_SYSCFG0_CPUCLK_300 0x3
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#define RT5350_SYSCFG0_DRAM_SIZE_SHIFT 12
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#define RT5350_SYSCFG0_DRAM_SIZE_MASK 7
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#define RT5350_SYSCFG0_DRAM_SIZE_2M 0
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#define RT5350_SYSCFG0_DRAM_SIZE_8M 1
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#define RT5350_SYSCFG0_DRAM_SIZE_16M 2
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#define RT5350_SYSCFG0_DRAM_SIZE_32M 3
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#define RT5350_SYSCFG0_DRAM_SIZE_64M 4
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/* multi function gpio pins */
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#define RT305X_GPIO_I2C_SD 1
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#define RT305X_GPIO_I2C_SCLK 2
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#define RT305X_GPIO_SPI_EN 3
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#define RT305X_GPIO_SPI_CLK 4
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/* GPIO 7-14 is shared between UART0, PCM and I2S interfaces */
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#define RT305X_GPIO_7 7
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#define RT305X_GPIO_10 10
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#define RT305X_GPIO_14 14
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#define RT305X_GPIO_UART1_TXD 15
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#define RT305X_GPIO_UART1_RXD 16
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#define RT305X_GPIO_JTAG_TDO 17
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#define RT305X_GPIO_JTAG_TDI 18
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#define RT305X_GPIO_MDIO_MDC 22
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#define RT305X_GPIO_MDIO_MDIO 23
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#define RT305X_GPIO_SDRAM_MD16 24
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#define RT305X_GPIO_SDRAM_MD31 39
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#define RT305X_GPIO_GE0_TXD0 40
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#define RT305X_GPIO_GE0_RXCLK 51
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#define RT3352_SYSC_REG_SYSCFG0 0x010
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#define RT3352_SYSC_REG_SYSCFG1 0x014
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#define RT3352_SYSC_REG_CLKCFG1 0x030
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#define RT3352_SYSC_REG_RSTCTRL 0x034
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#define RT3352_SYSC_REG_USB_PS 0x05c
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#define RT3352_CLKCFG0_XTAL_SEL BIT(20)
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#define RT3352_CLKCFG1_UPHY0_CLK_EN BIT(18)
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#define RT3352_CLKCFG1_UPHY1_CLK_EN BIT(20)
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#define RT3352_RSTCTRL_UHST BIT(22)
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#define RT3352_RSTCTRL_UDEV BIT(25)
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#define RT3352_SYSCFG1_USB0_HOST_MODE BIT(10)
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#define RT305X_SDRAM_BASE 0x00000000
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#define RT305X_MEM_SIZE_MIN 2
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#define RT305X_MEM_SIZE_MAX 64
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#define RT3352_MEM_SIZE_MIN 2
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#define RT3352_MEM_SIZE_MAX 256
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#endif
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