748 lines
13 KiB
ArmAsm
748 lines
13 KiB
ArmAsm
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2011-2012 by Broadcom Corporation
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*
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* Init for bmips 5000.
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* Used to init second core in dual core 5000's.
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*/
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#include <linux/init.h>
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#include <asm/asm.h>
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#include <asm/asmmacro.h>
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#include <asm/cacheops.h>
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#include <asm/regdef.h>
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#include <asm/mipsregs.h>
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#include <asm/stackframe.h>
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#include <asm/addrspace.h>
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#include <asm/hazards.h>
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#include <asm/bmips.h>
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#ifdef CONFIG_CPU_BMIPS5000
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#define cacheop(kva, size, linesize, op) \
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.set noreorder ; \
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addu t1, kva, size ; \
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subu t2, linesize, 1 ; \
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not t2 ; \
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and t0, kva, t2 ; \
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addiu t1, t1, -1 ; \
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and t1, t2 ; \
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9: cache op, 0(t0) ; \
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bne t0, t1, 9b ; \
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addu t0, linesize ; \
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.set reorder ;
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#define IS_SHIFT 22
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#define IL_SHIFT 19
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#define IA_SHIFT 16
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#define DS_SHIFT 13
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#define DL_SHIFT 10
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#define DA_SHIFT 7
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#define IS_MASK 7
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#define IL_MASK 7
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#define IA_MASK 7
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#define DS_MASK 7
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#define DL_MASK 7
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#define DA_MASK 7
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#define ICE_MASK 0x80000000
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#define DCE_MASK 0x40000000
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#define CP0_BRCM_CONFIG0 $22, 0
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#define CP0_BRCM_MODE $22, 1
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#define CP0_CONFIG_K0_MASK 7
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#define CP0_ICACHE_TAG_LO $28
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#define CP0_ICACHE_DATA_LO $28, 1
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#define CP0_DCACHE_TAG_LO $28, 2
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#define CP0_D_SEC_CACHE_DATA_LO $28, 3
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#define CP0_ICACHE_TAG_HI $29
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#define CP0_ICACHE_DATA_HI $29, 1
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#define CP0_DCACHE_TAG_HI $29, 2
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#define CP0_BRCM_MODE_Luc_MASK (1 << 11)
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#define CP0_BRCM_CONFIG0_CWF_MASK (1 << 20)
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#define CP0_BRCM_CONFIG0_TSE_MASK (1 << 19)
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#define CP0_BRCM_MODE_SET_MASK (1 << 7)
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#define CP0_BRCM_MODE_ClkRATIO_MASK (7 << 4)
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#define CP0_BRCM_MODE_BrPRED_MASK (3 << 24)
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#define CP0_BRCM_MODE_BrPRED_SHIFT 24
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#define CP0_BRCM_MODE_BrHIST_MASK (0x1f << 20)
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#define CP0_BRCM_MODE_BrHIST_SHIFT 20
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/* ZSC L2 Cache Register Access Register Definitions */
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#define BRCM_ZSC_ALL_REGS_SELECT 0x7 << 24
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#define BRCM_ZSC_CONFIG_REG 0 << 3
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#define BRCM_ZSC_REQ_BUFFER_REG 2 << 3
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#define BRCM_ZSC_RBUS_ADDR_MAPPING_REG0 4 << 3
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#define BRCM_ZSC_RBUS_ADDR_MAPPING_REG1 6 << 3
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#define BRCM_ZSC_RBUS_ADDR_MAPPING_REG2 8 << 3
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#define BRCM_ZSC_SCB0_ADDR_MAPPING_REG0 0xa << 3
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#define BRCM_ZSC_SCB0_ADDR_MAPPING_REG1 0xc << 3
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#define BRCM_ZSC_SCB1_ADDR_MAPPING_REG0 0xe << 3
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#define BRCM_ZSC_SCB1_ADDR_MAPPING_REG1 0x10 << 3
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#define BRCM_ZSC_CONFIG_LMB1En 1 << (15)
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#define BRCM_ZSC_CONFIG_LMB0En 1 << (14)
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/* branch predition values */
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#define BRCM_BrPRED_ALL_TAKEN (0x0)
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#define BRCM_BrPRED_ALL_NOT_TAKEN (0x1)
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#define BRCM_BrPRED_BHT_ENABLE (0x2)
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#define BRCM_BrPRED_PREDICT_BACKWARD (0x3)
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.align 2
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/*
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* Function: size_i_cache
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* Arguments: None
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* Returns: v0 = i cache size, v1 = I cache line size
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* Description: compute the I-cache size and I-cache line size
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* Trashes: v0, v1, a0, t0
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*
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* pseudo code:
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*
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*/
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LEAF(size_i_cache)
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.set noreorder
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mfc0 a0, CP0_CONFIG, 1
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move t0, a0
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/*
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* Determine sets per way: IS
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*
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* This field contains the number of sets (i.e., indices) per way of
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* the instruction cache:
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* i) 0x0: 64, ii) 0x1: 128, iii) 0x2: 256, iv) 0x3: 512, v) 0x4: 1k
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* vi) 0x5 - 0x7: Reserved.
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*/
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srl a0, a0, IS_SHIFT
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and a0, a0, IS_MASK
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/* sets per way = (64<<IS) */
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li v0, 0x40
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sllv v0, v0, a0
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/*
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* Determine line size
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*
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* This field contains the line size of the instruction cache:
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* i) 0x0: No I-cache present, i) 0x3: 16 bytes, ii) 0x4: 32 bytes, iii)
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* 0x5: 64 bytes, iv) the rest: Reserved.
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*/
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move a0, t0
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srl a0, a0, IL_SHIFT
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and a0, a0, IL_MASK
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beqz a0, no_i_cache
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nop
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/* line size = 2 ^ (IL+1) */
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addi a0, a0, 1
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li v1, 1
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sll v1, v1, a0
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/* v0 now have sets per way, multiply it by line size now
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* that will give the set size
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*/
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sll v0, v0, a0
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/*
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* Determine set associativity
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*
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* This field contains the set associativity of the instruction cache.
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* i) 0x0: Direct mapped, ii) 0x1: 2-way, iii) 0x2: 3-way, iv) 0x3:
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* 4-way, v) 0x4 - 0x7: Reserved.
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*/
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move a0, t0
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srl a0, a0, IA_SHIFT
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and a0, a0, IA_MASK
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addi a0, a0, 0x1
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/* v0 has the set size, multiply it by
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* set associativiy, to get the cache size
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*/
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multu v0, a0 /*multu is interlocked, so no need to insert nops */
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mflo v0
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b 1f
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nop
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no_i_cache:
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move v0, zero
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move v1, zero
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1:
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jr ra
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nop
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.set reorder
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END(size_i_cache)
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/*
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* Function: size_d_cache
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* Arguments: None
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* Returns: v0 = d cache size, v1 = d cache line size
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* Description: compute the D-cache size and D-cache line size.
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* Trashes: v0, v1, a0, t0
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*
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*/
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LEAF(size_d_cache)
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.set noreorder
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mfc0 a0, CP0_CONFIG, 1
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move t0, a0
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/*
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* Determine sets per way: IS
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*
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* This field contains the number of sets (i.e., indices) per way of
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* the instruction cache:
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* i) 0x0: 64, ii) 0x1: 128, iii) 0x2: 256, iv) 0x3: 512, v) 0x4: 1k
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* vi) 0x5 - 0x7: Reserved.
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*/
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srl a0, a0, DS_SHIFT
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and a0, a0, DS_MASK
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/* sets per way = (64<<IS) */
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li v0, 0x40
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sllv v0, v0, a0
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/*
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* Determine line size
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*
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* This field contains the line size of the instruction cache:
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* i) 0x0: No I-cache present, i) 0x3: 16 bytes, ii) 0x4: 32 bytes, iii)
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* 0x5: 64 bytes, iv) the rest: Reserved.
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*/
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move a0, t0
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srl a0, a0, DL_SHIFT
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and a0, a0, DL_MASK
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beqz a0, no_d_cache
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nop
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/* line size = 2 ^ (IL+1) */
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addi a0, a0, 1
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li v1, 1
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sll v1, v1, a0
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/* v0 now have sets per way, multiply it by line size now
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* that will give the set size
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*/
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sll v0, v0, a0
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/* determine set associativity
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*
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* This field contains the set associativity of the instruction cache.
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* i) 0x0: Direct mapped, ii) 0x1: 2-way, iii) 0x2: 3-way, iv) 0x3:
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* 4-way, v) 0x4 - 0x7: Reserved.
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*/
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move a0, t0
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srl a0, a0, DA_SHIFT
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and a0, a0, DA_MASK
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addi a0, a0, 0x1
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/* v0 has the set size, multiply it by
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* set associativiy, to get the cache size
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*/
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multu v0, a0 /*multu is interlocked, so no need to insert nops */
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mflo v0
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b 1f
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nop
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no_d_cache:
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move v0, zero
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move v1, zero
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1:
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jr ra
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nop
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.set reorder
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END(size_d_cache)
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/*
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* Function: enable_ID
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* Arguments: None
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* Returns: None
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* Description: Enable I and D caches, initialize I and D-caches, also set
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* hardware delay for d-cache (TP0).
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* Trashes: t0
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*
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*/
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.global enable_ID
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.ent enable_ID
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.set noreorder
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enable_ID:
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mfc0 t0, CP0_BRCM_CONFIG0
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or t0, t0, (ICE_MASK | DCE_MASK)
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mtc0 t0, CP0_BRCM_CONFIG0
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jr ra
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nop
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.end enable_ID
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.set reorder
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/*
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* Function: l1_init
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* Arguments: None
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* Returns: None
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* Description: Enable I and D caches, and initialize I and D-caches
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* Trashes: a0, v0, v1, t0, t1, t2, t8
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*
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*/
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.globl l1_init
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.ent l1_init
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.set noreorder
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l1_init:
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/* save return address */
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move t8, ra
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/* initialize I and D cache Data and Tag registers. */
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mtc0 zero, CP0_ICACHE_TAG_LO
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mtc0 zero, CP0_ICACHE_TAG_HI
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mtc0 zero, CP0_ICACHE_DATA_LO
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mtc0 zero, CP0_ICACHE_DATA_HI
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mtc0 zero, CP0_DCACHE_TAG_LO
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mtc0 zero, CP0_DCACHE_TAG_HI
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/* Enable Caches before Clearing. If the caches are disabled
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* then the cache operations to clear the cache will be ignored
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*/
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jal enable_ID
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nop
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jal size_i_cache /* v0 = i-cache size, v1 = i-cache line size */
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nop
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/* run uncached in kseg 1 */
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la k0, 1f
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lui k1, 0x2000
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or k0, k1, k0
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jr k0
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nop
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1:
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/*
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* set K0 cache mode
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*/
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mfc0 t0, CP0_CONFIG
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and t0, t0, ~CP0_CONFIG_K0_MASK
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or t0, t0, 3 /* Write Back mode */
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mtc0 t0, CP0_CONFIG
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/*
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* Initialize instruction cache.
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*/
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li a0, KSEG0
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cacheop(a0, v0, v1, Index_Store_Tag_I)
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/*
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* Now we can run from I-$, kseg 0
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*/
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la k0, 1f
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lui k1, 0x2000
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or k0, k1, k0
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xor k0, k1, k0
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jr k0
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nop
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1:
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/*
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* Initialize data cache.
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*/
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jal size_d_cache /* v0 = d-cache size, v1 = d-cache line size */
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nop
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li a0, KSEG0
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cacheop(a0, v0, v1, Index_Store_Tag_D)
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jr t8
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nop
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.end l1_init
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.set reorder
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/*
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* Function: set_other_config
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* Arguments: none
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* Returns: None
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* Description: initialize other remainder configuration to defaults.
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* Trashes: t0, t1
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*
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* pseudo code:
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*
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*/
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LEAF(set_other_config)
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.set noreorder
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/* enable Bus error for I-fetch */
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mfc0 t0, CP0_CACHEERR, 0
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li t1, 0x4
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or t0, t1
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mtc0 t0, CP0_CACHEERR, 0
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/* enable Bus error for Load */
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mfc0 t0, CP0_CACHEERR, 1
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li t1, 0x4
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or t0, t1
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mtc0 t0, CP0_CACHEERR, 1
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/* enable Bus Error for Store */
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mfc0 t0, CP0_CACHEERR, 2
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li t1, 0x4
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or t0, t1
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mtc0 t0, CP0_CACHEERR, 2
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jr ra
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nop
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.set reorder
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END(set_other_config)
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/*
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* Function: set_branch_pred
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* Arguments: none
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* Returns: None
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* Description:
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* Trashes: t0, t1
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*
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* pseudo code:
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*
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*/
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LEAF(set_branch_pred)
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.set noreorder
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mfc0 t0, CP0_BRCM_MODE
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li t1, ~(CP0_BRCM_MODE_BrPRED_MASK | CP0_BRCM_MODE_BrHIST_MASK )
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and t0, t0, t1
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/* enable Branch prediction */
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li t1, BRCM_BrPRED_BHT_ENABLE
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sll t1, CP0_BRCM_MODE_BrPRED_SHIFT
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or t0, t0, t1
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/* set history count to 8 */
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li t1, 8
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sll t1, CP0_BRCM_MODE_BrHIST_SHIFT
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or t0, t0, t1
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mtc0 t0, CP0_BRCM_MODE
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jr ra
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nop
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.set reorder
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END(set_branch_pred)
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/*
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* Function: set_luc
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* Arguments: set link uncached.
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* Returns: None
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* Description:
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* Trashes: t0, t1
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*
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*/
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LEAF(set_luc)
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.set noreorder
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mfc0 t0, CP0_BRCM_MODE
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li t1, ~(CP0_BRCM_MODE_Luc_MASK)
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and t0, t0, t1
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/* set Luc */
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ori t0, t0, CP0_BRCM_MODE_Luc_MASK
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mtc0 t0, CP0_BRCM_MODE
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jr ra
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nop
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.set reorder
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END(set_luc)
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/*
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* Function: set_cwf_tse
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* Arguments: set CWF and TSE bits
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* Returns: None
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* Description:
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* Trashes: t0, t1
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*
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*/
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LEAF(set_cwf_tse)
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.set noreorder
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mfc0 t0, CP0_BRCM_CONFIG0
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li t1, (CP0_BRCM_CONFIG0_CWF_MASK | CP0_BRCM_CONFIG0_TSE_MASK)
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or t0, t0, t1
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mtc0 t0, CP0_BRCM_CONFIG0
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jr ra
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nop
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.set reorder
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END(set_cwf_tse)
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/*
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* Function: set_clock_ratio
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* Arguments: set clock ratio specified by a0
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* Returns: None
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* Description:
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* Trashes: v0, v1, a0, a1
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*
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* pseudo code:
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*
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*/
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LEAF(set_clock_ratio)
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.set noreorder
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mfc0 t0, CP0_BRCM_MODE
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li t1, ~(CP0_BRCM_MODE_SET_MASK | CP0_BRCM_MODE_ClkRATIO_MASK)
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and t0, t0, t1
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li t1, CP0_BRCM_MODE_SET_MASK
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or t0, t0, t1
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or t0, t0, a0
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mtc0 t0, CP0_BRCM_MODE
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jr ra
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nop
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.set reorder
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END(set_clock_ratio)
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/*
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* Function: set_zephyr
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* Arguments: None
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* Returns: None
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* Description: Set any zephyr bits
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* Trashes: t0 & t1
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*
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*/
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LEAF(set_zephyr)
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.set noreorder
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/* enable read/write of CP0 #22 sel. 8 */
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li t0, 0x5a455048
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.word 0x4088b00f /* mtc0 t0, $22, 15 */
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|
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.word 0x4008b008 /* mfc0 t0, $22, 8 */
|
|
li t1, 0x09008000 /* turn off pref, jtb */
|
|
or t0, t0, t1
|
|
.word 0x4088b008 /* mtc0 t0, $22, 8 */
|
|
sync
|
|
|
|
/* disable read/write of CP0 #22 sel 8 */
|
|
li t0, 0x0
|
|
.word 0x4088b00f /* mtc0 t0, $22, 15 */
|
|
|
|
|
|
jr ra
|
|
nop
|
|
.set reorder
|
|
|
|
END(set_zephyr)
|
|
|
|
|
|
/*
|
|
* Function: set_llmb
|
|
* Arguments: a0=0 disable llmb, a0=1 enables llmb
|
|
* Returns: None
|
|
* Description:
|
|
* Trashes: t0, t1, t2
|
|
*
|
|
* pseudo code:
|
|
*
|
|
*/
|
|
LEAF(set_llmb)
|
|
.set noreorder
|
|
|
|
li t2, 0x90000000 | BRCM_ZSC_ALL_REGS_SELECT | BRCM_ZSC_CONFIG_REG
|
|
sync
|
|
cache 0x7, 0x0(t2)
|
|
sync
|
|
mfc0 t0, CP0_D_SEC_CACHE_DATA_LO
|
|
li t1, ~(BRCM_ZSC_CONFIG_LMB1En | BRCM_ZSC_CONFIG_LMB0En)
|
|
and t0, t0, t1
|
|
|
|
beqz a0, svlmb
|
|
nop
|
|
|
|
enable_lmb:
|
|
li t1, (BRCM_ZSC_CONFIG_LMB1En | BRCM_ZSC_CONFIG_LMB0En)
|
|
or t0, t0, t1
|
|
|
|
svlmb:
|
|
mtc0 t0, CP0_D_SEC_CACHE_DATA_LO
|
|
sync
|
|
cache 0xb, 0x0(t2)
|
|
sync
|
|
|
|
jr ra
|
|
nop
|
|
.set reorder
|
|
|
|
END(set_llmb)
|
|
/*
|
|
* Function: core_init
|
|
* Arguments: none
|
|
* Returns: None
|
|
* Description: initialize core related configuration
|
|
* Trashes: v0,v1,a0,a1,t8
|
|
*
|
|
* pseudo code:
|
|
*
|
|
*/
|
|
.globl core_init
|
|
.ent core_init
|
|
.set noreorder
|
|
core_init:
|
|
move t8, ra
|
|
|
|
/* set Zephyr bits. */
|
|
bal set_zephyr
|
|
nop
|
|
|
|
/* set low latency memory bus */
|
|
li a0, 1
|
|
bal set_llmb
|
|
nop
|
|
|
|
/* set branch prediction (TP0 only) */
|
|
bal set_branch_pred
|
|
nop
|
|
|
|
/* set link uncached */
|
|
bal set_luc
|
|
nop
|
|
|
|
/* set CWF and TSE */
|
|
bal set_cwf_tse
|
|
nop
|
|
|
|
/*
|
|
*set clock ratio by setting 1 to 'set'
|
|
* and 0 to ClkRatio, (TP0 only)
|
|
*/
|
|
li a0, 0
|
|
bal set_clock_ratio
|
|
nop
|
|
|
|
/* set other configuration to defaults */
|
|
bal set_other_config
|
|
nop
|
|
|
|
move ra, t8
|
|
jr ra
|
|
nop
|
|
|
|
.set reorder
|
|
.end core_init
|
|
|
|
/*
|
|
* Function: clear_jump_target_buffer
|
|
* Arguments: None
|
|
* Returns: None
|
|
* Description:
|
|
* Trashes: t0, t1, t2
|
|
*
|
|
*/
|
|
#define RESET_CALL_RETURN_STACK_THIS_THREAD (0x06<<16)
|
|
#define RESET_JUMP_TARGET_BUFFER_THIS_THREAD (0x04<<16)
|
|
#define JTB_CS_CNTL_MASK (0xFF<<16)
|
|
|
|
.globl clear_jump_target_buffer
|
|
.ent clear_jump_target_buffer
|
|
.set noreorder
|
|
clear_jump_target_buffer:
|
|
|
|
mfc0 t0, $22, 2
|
|
nop
|
|
nop
|
|
|
|
li t1, ~JTB_CS_CNTL_MASK
|
|
and t0, t0, t1
|
|
li t2, RESET_CALL_RETURN_STACK_THIS_THREAD
|
|
or t0, t0, t2
|
|
mtc0 t0, $22, 2
|
|
nop
|
|
nop
|
|
|
|
and t0, t0, t1
|
|
li t2, RESET_JUMP_TARGET_BUFFER_THIS_THREAD
|
|
or t0, t0, t2
|
|
mtc0 t0, $22, 2
|
|
nop
|
|
nop
|
|
jr ra
|
|
nop
|
|
|
|
.end clear_jump_target_buffer
|
|
.set reorder
|
|
/*
|
|
* Function: bmips_cache_init
|
|
* Arguments: None
|
|
* Returns: None
|
|
* Description: Enable I and D caches, and initialize I and D-caches
|
|
* Trashes: v0, v1, t0, t1, t2, t5, t7, t8
|
|
*
|
|
*/
|
|
.globl bmips_5xxx_init
|
|
.ent bmips_5xxx_init
|
|
.set noreorder
|
|
bmips_5xxx_init:
|
|
|
|
/* save return address and A0 */
|
|
move t7, ra
|
|
move t5, a0
|
|
|
|
jal l1_init
|
|
nop
|
|
|
|
jal core_init
|
|
nop
|
|
|
|
jal clear_jump_target_buffer
|
|
nop
|
|
|
|
mtc0 zero, CP0_CAUSE
|
|
|
|
move a0, t5
|
|
jr t7
|
|
nop
|
|
|
|
.end bmips_5xxx_init
|
|
.set reorder
|
|
|
|
|
|
#endif
|