331 lines
8.7 KiB
C
331 lines
8.7 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* ip30-irq.c: Highlevel interrupt handling for IP30 architecture.
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*/
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#include <linux/errno.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/irqdomain.h>
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#include <linux/percpu.h>
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#include <linux/spinlock.h>
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#include <linux/tick.h>
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#include <linux/types.h>
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#include <asm/irq_cpu.h>
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#include <asm/sgi/heart.h>
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#include "ip30-common.h"
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struct heart_irq_data {
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u64 *irq_mask;
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int cpu;
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};
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static DECLARE_BITMAP(heart_irq_map, HEART_NUM_IRQS);
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static DEFINE_PER_CPU(unsigned long, irq_enable_mask);
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static inline int heart_alloc_int(void)
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{
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int bit;
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again:
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bit = find_first_zero_bit(heart_irq_map, HEART_NUM_IRQS);
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if (bit >= HEART_NUM_IRQS)
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return -ENOSPC;
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if (test_and_set_bit(bit, heart_irq_map))
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goto again;
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return bit;
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}
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static void ip30_error_irq(struct irq_desc *desc)
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{
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u64 pending, mask, cause, error_irqs, err_reg;
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int cpu = smp_processor_id();
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int i;
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pending = heart_read(&heart_regs->isr);
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mask = heart_read(&heart_regs->imr[cpu]);
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cause = heart_read(&heart_regs->cause);
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error_irqs = (pending & HEART_L4_INT_MASK & mask);
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/* Bail if there's nothing to process (how did we get here, then?) */
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if (unlikely(!error_irqs))
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return;
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/* Prevent any of the error IRQs from firing again. */
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heart_write(mask & ~(pending), &heart_regs->imr[cpu]);
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/* Ack all error IRQs. */
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heart_write(HEART_L4_INT_MASK, &heart_regs->clear_isr);
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/*
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* If we also have a cause value, then something happened, so loop
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* through the error IRQs and report a "heart attack" for each one
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* and print the value of the HEART cause register. This is really
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* primitive right now, but it should hopefully work until a more
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* robust error handling routine can be put together.
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*
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* Refer to heart.h for the HC_* macros to work out the cause
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* that got us here.
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*/
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if (cause) {
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pr_alert("IP30: CPU%d: HEART ATTACK! ISR = 0x%.16llx, IMR = 0x%.16llx, CAUSE = 0x%.16llx\n",
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cpu, pending, mask, cause);
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if (cause & HC_COR_MEM_ERR) {
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err_reg = heart_read(&heart_regs->mem_err_addr);
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pr_alert(" HEART_MEMERR_ADDR = 0x%.16llx\n", err_reg);
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}
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/* i = 63; i >= 51; i-- */
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for (i = HEART_ERR_MASK_END; i >= HEART_ERR_MASK_START; i--)
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if ((pending >> i) & 1)
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pr_alert(" HEART Error IRQ #%d\n", i);
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/* XXX: Seems possible to loop forever here, so panic(). */
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panic("IP30: Fatal Error !\n");
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}
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/* Unmask the error IRQs. */
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heart_write(mask, &heart_regs->imr[cpu]);
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}
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static void ip30_normal_irq(struct irq_desc *desc)
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{
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int cpu = smp_processor_id();
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struct irq_domain *domain;
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u64 pend, mask;
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int ret;
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pend = heart_read(&heart_regs->isr);
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mask = (heart_read(&heart_regs->imr[cpu]) &
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(HEART_L0_INT_MASK | HEART_L1_INT_MASK | HEART_L2_INT_MASK));
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pend &= mask;
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if (unlikely(!pend))
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return;
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#ifdef CONFIG_SMP
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if (pend & BIT_ULL(HEART_L2_INT_RESCHED_CPU_0)) {
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heart_write(BIT_ULL(HEART_L2_INT_RESCHED_CPU_0),
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&heart_regs->clear_isr);
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scheduler_ipi();
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} else if (pend & BIT_ULL(HEART_L2_INT_RESCHED_CPU_1)) {
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heart_write(BIT_ULL(HEART_L2_INT_RESCHED_CPU_1),
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&heart_regs->clear_isr);
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scheduler_ipi();
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} else if (pend & BIT_ULL(HEART_L2_INT_CALL_CPU_0)) {
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heart_write(BIT_ULL(HEART_L2_INT_CALL_CPU_0),
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&heart_regs->clear_isr);
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generic_smp_call_function_interrupt();
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} else if (pend & BIT_ULL(HEART_L2_INT_CALL_CPU_1)) {
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heart_write(BIT_ULL(HEART_L2_INT_CALL_CPU_1),
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&heart_regs->clear_isr);
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generic_smp_call_function_interrupt();
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} else
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#endif
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{
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domain = irq_desc_get_handler_data(desc);
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ret = generic_handle_domain_irq(domain, __ffs(pend));
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if (ret)
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spurious_interrupt();
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}
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}
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static void ip30_ack_heart_irq(struct irq_data *d)
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{
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heart_write(BIT_ULL(d->hwirq), &heart_regs->clear_isr);
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}
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static void ip30_mask_heart_irq(struct irq_data *d)
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{
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struct heart_irq_data *hd = irq_data_get_irq_chip_data(d);
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unsigned long *mask = &per_cpu(irq_enable_mask, hd->cpu);
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clear_bit(d->hwirq, mask);
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heart_write(*mask, &heart_regs->imr[hd->cpu]);
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}
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static void ip30_mask_and_ack_heart_irq(struct irq_data *d)
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{
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struct heart_irq_data *hd = irq_data_get_irq_chip_data(d);
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unsigned long *mask = &per_cpu(irq_enable_mask, hd->cpu);
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clear_bit(d->hwirq, mask);
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heart_write(*mask, &heart_regs->imr[hd->cpu]);
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heart_write(BIT_ULL(d->hwirq), &heart_regs->clear_isr);
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}
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static void ip30_unmask_heart_irq(struct irq_data *d)
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{
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struct heart_irq_data *hd = irq_data_get_irq_chip_data(d);
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unsigned long *mask = &per_cpu(irq_enable_mask, hd->cpu);
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set_bit(d->hwirq, mask);
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heart_write(*mask, &heart_regs->imr[hd->cpu]);
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}
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static int ip30_set_heart_irq_affinity(struct irq_data *d,
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const struct cpumask *mask, bool force)
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{
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struct heart_irq_data *hd = irq_data_get_irq_chip_data(d);
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if (!hd)
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return -EINVAL;
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if (irqd_is_started(d))
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ip30_mask_and_ack_heart_irq(d);
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hd->cpu = cpumask_first_and(mask, cpu_online_mask);
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if (irqd_is_started(d))
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ip30_unmask_heart_irq(d);
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irq_data_update_effective_affinity(d, cpumask_of(hd->cpu));
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return 0;
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}
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static struct irq_chip heart_irq_chip = {
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.name = "HEART",
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.irq_ack = ip30_ack_heart_irq,
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.irq_mask = ip30_mask_heart_irq,
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.irq_mask_ack = ip30_mask_and_ack_heart_irq,
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.irq_unmask = ip30_unmask_heart_irq,
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.irq_set_affinity = ip30_set_heart_irq_affinity,
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};
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static int heart_domain_alloc(struct irq_domain *domain, unsigned int virq,
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unsigned int nr_irqs, void *arg)
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{
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struct irq_alloc_info *info = arg;
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struct heart_irq_data *hd;
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int hwirq;
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if (nr_irqs > 1 || !info)
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return -EINVAL;
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hd = kzalloc(sizeof(*hd), GFP_KERNEL);
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if (!hd)
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return -ENOMEM;
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hwirq = heart_alloc_int();
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if (hwirq < 0) {
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kfree(hd);
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return -EAGAIN;
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}
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irq_domain_set_info(domain, virq, hwirq, &heart_irq_chip, hd,
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handle_level_irq, NULL, NULL);
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return 0;
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}
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static void heart_domain_free(struct irq_domain *domain,
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unsigned int virq, unsigned int nr_irqs)
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{
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struct irq_data *irqd;
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if (nr_irqs > 1)
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return;
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irqd = irq_domain_get_irq_data(domain, virq);
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if (irqd) {
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clear_bit(irqd->hwirq, heart_irq_map);
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kfree(irqd->chip_data);
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}
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}
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static const struct irq_domain_ops heart_domain_ops = {
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.alloc = heart_domain_alloc,
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.free = heart_domain_free,
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};
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void __init ip30_install_ipi(void)
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{
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int cpu = smp_processor_id();
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unsigned long *mask = &per_cpu(irq_enable_mask, cpu);
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set_bit(HEART_L2_INT_RESCHED_CPU_0 + cpu, mask);
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heart_write(BIT_ULL(HEART_L2_INT_RESCHED_CPU_0 + cpu),
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&heart_regs->clear_isr);
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set_bit(HEART_L2_INT_CALL_CPU_0 + cpu, mask);
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heart_write(BIT_ULL(HEART_L2_INT_CALL_CPU_0 + cpu),
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&heart_regs->clear_isr);
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heart_write(*mask, &heart_regs->imr[cpu]);
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}
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void __init arch_init_irq(void)
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{
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struct irq_domain *domain;
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struct fwnode_handle *fn;
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unsigned long *mask;
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int i;
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mips_cpu_irq_init();
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/* Mask all IRQs. */
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heart_write(HEART_CLR_ALL_MASK, &heart_regs->imr[0]);
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heart_write(HEART_CLR_ALL_MASK, &heart_regs->imr[1]);
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heart_write(HEART_CLR_ALL_MASK, &heart_regs->imr[2]);
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heart_write(HEART_CLR_ALL_MASK, &heart_regs->imr[3]);
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/* Ack everything. */
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heart_write(HEART_ACK_ALL_MASK, &heart_regs->clear_isr);
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/* Enable specific HEART error IRQs for each CPU. */
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mask = &per_cpu(irq_enable_mask, 0);
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*mask |= HEART_CPU0_ERR_MASK;
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heart_write(*mask, &heart_regs->imr[0]);
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mask = &per_cpu(irq_enable_mask, 1);
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*mask |= HEART_CPU1_ERR_MASK;
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heart_write(*mask, &heart_regs->imr[1]);
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/*
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* Some HEART bits are reserved by hardware or by software convention.
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* Mark these as reserved right away so they won't be accidentally
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* used later.
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*/
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set_bit(HEART_L0_INT_GENERIC, heart_irq_map);
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set_bit(HEART_L0_INT_FLOW_CTRL_HWTR_0, heart_irq_map);
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set_bit(HEART_L0_INT_FLOW_CTRL_HWTR_1, heart_irq_map);
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set_bit(HEART_L2_INT_RESCHED_CPU_0, heart_irq_map);
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set_bit(HEART_L2_INT_RESCHED_CPU_1, heart_irq_map);
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set_bit(HEART_L2_INT_CALL_CPU_0, heart_irq_map);
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set_bit(HEART_L2_INT_CALL_CPU_1, heart_irq_map);
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set_bit(HEART_L3_INT_TIMER, heart_irq_map);
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/* Reserve the error interrupts (#51 to #63). */
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for (i = HEART_L4_INT_XWID_ERR_9; i <= HEART_L4_INT_HEART_EXCP; i++)
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set_bit(i, heart_irq_map);
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fn = irq_domain_alloc_named_fwnode("HEART");
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WARN_ON(fn == NULL);
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if (!fn)
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return;
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domain = irq_domain_create_linear(fn, HEART_NUM_IRQS,
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&heart_domain_ops, NULL);
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WARN_ON(domain == NULL);
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if (!domain)
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return;
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irq_set_default_host(domain);
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irq_set_percpu_devid(IP30_HEART_L0_IRQ);
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irq_set_chained_handler_and_data(IP30_HEART_L0_IRQ, ip30_normal_irq,
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domain);
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irq_set_percpu_devid(IP30_HEART_L1_IRQ);
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irq_set_chained_handler_and_data(IP30_HEART_L1_IRQ, ip30_normal_irq,
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domain);
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irq_set_percpu_devid(IP30_HEART_L2_IRQ);
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irq_set_chained_handler_and_data(IP30_HEART_L2_IRQ, ip30_normal_irq,
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domain);
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irq_set_percpu_devid(IP30_HEART_ERR_IRQ);
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irq_set_chained_handler_and_data(IP30_HEART_ERR_IRQ, ip30_error_irq,
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domain);
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}
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