187 lines
5.8 KiB
C
187 lines
5.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_POWERPC_NOHASH_32_PTE_8xx_H
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#define _ASM_POWERPC_NOHASH_32_PTE_8xx_H
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#ifdef __KERNEL__
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/*
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* The PowerPC MPC8xx uses a TLB with hardware assisted, software tablewalk.
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* We also use the two level tables, but we can put the real bits in them
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* needed for the TLB and tablewalk. These definitions require Mx_CTR.PPM = 0,
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* Mx_CTR.PPCS = 0, and MD_CTR.TWAM = 1. The level 2 descriptor has
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* additional page protection (when Mx_CTR.PPCS = 1) that allows TLB hit
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* based upon user/super access. The TLB does not have accessed nor write
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* protect. We assume that if the TLB get loaded with an entry it is
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* accessed, and overload the changed bit for write protect. We use
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* two bits in the software pte that are supposed to be set to zero in
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* the TLB entry (24 and 25) for these indicators. Although the level 1
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* descriptor contains the guarded and writethrough/copyback bits, we can
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* set these at the page level since they get copied from the Mx_TWC
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* register when the TLB entry is loaded. We will use bit 27 for guard, since
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* that is where it exists in the MD_TWC, and bit 26 for writethrough.
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* These will get masked from the level 2 descriptor at TLB load time, and
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* copied to the MD_TWC before it gets loaded.
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* Large page sizes added. We currently support two sizes, 4K and 8M.
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* This also allows a TLB hander optimization because we can directly
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* load the PMD into MD_TWC. The 8M pages are only used for kernel
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* mapping of well known areas. The PMD (PGD) entries contain control
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* flags in addition to the address, so care must be taken that the
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* software no longer assumes these are only pointers.
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*/
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/* Definitions for 8xx embedded chips. */
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#define _PAGE_PRESENT 0x0001 /* V: Page is valid */
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#define _PAGE_NO_CACHE 0x0002 /* CI: cache inhibit */
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#define _PAGE_SH 0x0004 /* SH: No ASID (context) compare */
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#define _PAGE_SPS 0x0008 /* SPS: Small Page Size (1 if 16k, 512k or 8M)*/
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#define _PAGE_DIRTY 0x0100 /* C: page changed */
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/* These 4 software bits must be masked out when the L2 entry is loaded
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* into the TLB.
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*/
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#define _PAGE_GUARDED 0x0010 /* Copied to L1 G entry in DTLB */
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#define _PAGE_ACCESSED 0x0020 /* Copied to L1 APG 1 entry in I/DTLB */
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#define _PAGE_EXEC 0x0040 /* Copied to PP (bit 21) in ITLB */
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#define _PAGE_SPECIAL 0x0080 /* SW entry */
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#define _PAGE_NA 0x0200 /* Supervisor NA, User no access */
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#define _PAGE_RO 0x0600 /* Supervisor RO, User no access */
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#define _PAGE_HUGE 0x0800 /* Copied to L1 PS bit 29 */
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/* cache related flags non existing on 8xx */
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#define _PAGE_COHERENT 0
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#define _PAGE_WRITETHRU 0
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#define _PAGE_KERNEL_RO (_PAGE_SH | _PAGE_RO)
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#define _PAGE_KERNEL_ROX (_PAGE_SH | _PAGE_RO | _PAGE_EXEC)
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#define _PAGE_KERNEL_RW (_PAGE_SH | _PAGE_DIRTY)
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#define _PAGE_KERNEL_RWX (_PAGE_SH | _PAGE_DIRTY | _PAGE_EXEC)
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#define _PMD_PRESENT 0x0001
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#define _PMD_PRESENT_MASK _PMD_PRESENT
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#define _PMD_BAD 0x0f90
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#define _PMD_PAGE_MASK 0x000c
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#define _PMD_PAGE_8M 0x000c
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#define _PMD_PAGE_512K 0x0004
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#define _PMD_ACCESSED 0x0020 /* APG 1 */
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#define _PMD_USER 0x0040 /* APG 2 */
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#define _PTE_NONE_MASK 0
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#ifdef CONFIG_PPC_16K_PAGES
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#define _PAGE_PSIZE _PAGE_SPS
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#else
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#define _PAGE_PSIZE 0
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#endif
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#define _PAGE_BASE_NC (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_PSIZE)
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#define _PAGE_BASE (_PAGE_BASE_NC)
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/* Permission masks used to generate the __P and __S table */
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#define PAGE_NONE __pgprot(_PAGE_BASE | _PAGE_NA)
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#define PAGE_SHARED __pgprot(_PAGE_BASE)
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#define PAGE_SHARED_X __pgprot(_PAGE_BASE | _PAGE_EXEC)
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#define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_RO)
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#define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_RO | _PAGE_EXEC)
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#define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_RO)
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#define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_RO | _PAGE_EXEC)
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#ifndef __ASSEMBLY__
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static inline pte_t pte_wrprotect(pte_t pte)
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{
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return __pte(pte_val(pte) | _PAGE_RO);
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}
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#define pte_wrprotect pte_wrprotect
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static inline int pte_write(pte_t pte)
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{
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return !(pte_val(pte) & _PAGE_RO);
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}
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#define pte_write pte_write
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static inline pte_t pte_mkwrite(pte_t pte)
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{
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return __pte(pte_val(pte) & ~_PAGE_RO);
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}
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#define pte_mkwrite pte_mkwrite
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static inline bool pte_user(pte_t pte)
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{
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return !(pte_val(pte) & _PAGE_SH);
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}
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#define pte_user pte_user
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static inline pte_t pte_mkprivileged(pte_t pte)
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{
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return __pte(pte_val(pte) | _PAGE_SH);
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}
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#define pte_mkprivileged pte_mkprivileged
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static inline pte_t pte_mkuser(pte_t pte)
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{
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return __pte(pte_val(pte) & ~_PAGE_SH);
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}
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#define pte_mkuser pte_mkuser
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static inline pte_t pte_mkhuge(pte_t pte)
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{
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return __pte(pte_val(pte) | _PAGE_SPS | _PAGE_HUGE);
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}
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#define pte_mkhuge pte_mkhuge
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static inline pte_basic_t pte_update(struct mm_struct *mm, unsigned long addr, pte_t *p,
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unsigned long clr, unsigned long set, int huge);
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static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
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{
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pte_update(mm, addr, ptep, 0, _PAGE_RO, 0);
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}
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#define ptep_set_wrprotect ptep_set_wrprotect
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static inline void __ptep_set_access_flags(struct vm_area_struct *vma, pte_t *ptep,
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pte_t entry, unsigned long address, int psize)
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{
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unsigned long set = pte_val(entry) & (_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_EXEC);
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unsigned long clr = ~pte_val(entry) & _PAGE_RO;
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int huge = psize > mmu_virtual_psize ? 1 : 0;
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pte_update(vma->vm_mm, address, ptep, clr, set, huge);
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flush_tlb_page(vma, address);
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}
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#define __ptep_set_access_flags __ptep_set_access_flags
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static inline unsigned long pgd_leaf_size(pgd_t pgd)
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{
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if (pgd_val(pgd) & _PMD_PAGE_8M)
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return SZ_8M;
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return SZ_4M;
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}
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#define pgd_leaf_size pgd_leaf_size
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static inline unsigned long pte_leaf_size(pte_t pte)
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{
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pte_basic_t val = pte_val(pte);
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if (val & _PAGE_HUGE)
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return SZ_512K;
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if (val & _PAGE_SPS)
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return SZ_16K;
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return SZ_4K;
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}
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#define pte_leaf_size pte_leaf_size
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#endif
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#endif /* __KERNEL__ */
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#endif /* _ASM_POWERPC_NOHASH_32_PTE_8xx_H */
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