1141 lines
28 KiB
C
1141 lines
28 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2019 Western Digital Corporation or its affiliates.
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*
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* Authors:
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* Anup Patel <anup.patel@wdc.com>
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*/
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#include <linux/bitops.h>
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#include <linux/entry-kvm.h>
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#include <linux/errno.h>
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#include <linux/err.h>
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#include <linux/kdebug.h>
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#include <linux/module.h>
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#include <linux/percpu.h>
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#include <linux/uaccess.h>
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#include <linux/vmalloc.h>
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#include <linux/sched/signal.h>
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#include <linux/fs.h>
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#include <linux/kvm_host.h>
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#include <asm/csr.h>
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#include <asm/cacheflush.h>
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#include <asm/hwcap.h>
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#include <asm/sbi.h>
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const struct _kvm_stats_desc kvm_vcpu_stats_desc[] = {
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KVM_GENERIC_VCPU_STATS(),
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STATS_DESC_COUNTER(VCPU, ecall_exit_stat),
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STATS_DESC_COUNTER(VCPU, wfi_exit_stat),
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STATS_DESC_COUNTER(VCPU, mmio_exit_user),
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STATS_DESC_COUNTER(VCPU, mmio_exit_kernel),
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STATS_DESC_COUNTER(VCPU, csr_exit_user),
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STATS_DESC_COUNTER(VCPU, csr_exit_kernel),
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STATS_DESC_COUNTER(VCPU, signal_exits),
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STATS_DESC_COUNTER(VCPU, exits)
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};
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const struct kvm_stats_header kvm_vcpu_stats_header = {
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.name_size = KVM_STATS_NAME_SIZE,
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.num_desc = ARRAY_SIZE(kvm_vcpu_stats_desc),
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.id_offset = sizeof(struct kvm_stats_header),
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.desc_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE,
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.data_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE +
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sizeof(kvm_vcpu_stats_desc),
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};
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#define KVM_RISCV_BASE_ISA_MASK GENMASK(25, 0)
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#define KVM_ISA_EXT_ARR(ext) [KVM_RISCV_ISA_EXT_##ext] = RISCV_ISA_EXT_##ext
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/* Mapping between KVM ISA Extension ID & Host ISA extension ID */
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static const unsigned long kvm_isa_ext_arr[] = {
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[KVM_RISCV_ISA_EXT_A] = RISCV_ISA_EXT_a,
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[KVM_RISCV_ISA_EXT_C] = RISCV_ISA_EXT_c,
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[KVM_RISCV_ISA_EXT_D] = RISCV_ISA_EXT_d,
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[KVM_RISCV_ISA_EXT_F] = RISCV_ISA_EXT_f,
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[KVM_RISCV_ISA_EXT_H] = RISCV_ISA_EXT_h,
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[KVM_RISCV_ISA_EXT_I] = RISCV_ISA_EXT_i,
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[KVM_RISCV_ISA_EXT_M] = RISCV_ISA_EXT_m,
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KVM_ISA_EXT_ARR(SSTC),
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KVM_ISA_EXT_ARR(SVINVAL),
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KVM_ISA_EXT_ARR(SVPBMT),
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KVM_ISA_EXT_ARR(ZIHINTPAUSE),
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KVM_ISA_EXT_ARR(ZICBOM),
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};
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static unsigned long kvm_riscv_vcpu_base2isa_ext(unsigned long base_ext)
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{
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unsigned long i;
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for (i = 0; i < KVM_RISCV_ISA_EXT_MAX; i++) {
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if (kvm_isa_ext_arr[i] == base_ext)
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return i;
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}
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return KVM_RISCV_ISA_EXT_MAX;
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}
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static bool kvm_riscv_vcpu_isa_enable_allowed(unsigned long ext)
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{
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switch (ext) {
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case KVM_RISCV_ISA_EXT_H:
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return false;
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default:
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break;
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}
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return true;
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}
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static bool kvm_riscv_vcpu_isa_disable_allowed(unsigned long ext)
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{
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switch (ext) {
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case KVM_RISCV_ISA_EXT_A:
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case KVM_RISCV_ISA_EXT_C:
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case KVM_RISCV_ISA_EXT_I:
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case KVM_RISCV_ISA_EXT_M:
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case KVM_RISCV_ISA_EXT_SSTC:
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case KVM_RISCV_ISA_EXT_SVINVAL:
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case KVM_RISCV_ISA_EXT_ZIHINTPAUSE:
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return false;
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default:
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break;
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}
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return true;
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}
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static void kvm_riscv_reset_vcpu(struct kvm_vcpu *vcpu)
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{
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struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr;
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struct kvm_vcpu_csr *reset_csr = &vcpu->arch.guest_reset_csr;
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struct kvm_cpu_context *cntx = &vcpu->arch.guest_context;
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struct kvm_cpu_context *reset_cntx = &vcpu->arch.guest_reset_context;
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bool loaded;
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/**
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* The preemption should be disabled here because it races with
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* kvm_sched_out/kvm_sched_in(called from preempt notifiers) which
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* also calls vcpu_load/put.
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*/
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get_cpu();
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loaded = (vcpu->cpu != -1);
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if (loaded)
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kvm_arch_vcpu_put(vcpu);
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vcpu->arch.last_exit_cpu = -1;
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memcpy(csr, reset_csr, sizeof(*csr));
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memcpy(cntx, reset_cntx, sizeof(*cntx));
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kvm_riscv_vcpu_fp_reset(vcpu);
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kvm_riscv_vcpu_timer_reset(vcpu);
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WRITE_ONCE(vcpu->arch.irqs_pending, 0);
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WRITE_ONCE(vcpu->arch.irqs_pending_mask, 0);
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kvm_riscv_vcpu_pmu_reset(vcpu);
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vcpu->arch.hfence_head = 0;
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vcpu->arch.hfence_tail = 0;
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memset(vcpu->arch.hfence_queue, 0, sizeof(vcpu->arch.hfence_queue));
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/* Reset the guest CSRs for hotplug usecase */
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if (loaded)
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kvm_arch_vcpu_load(vcpu, smp_processor_id());
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put_cpu();
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}
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int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id)
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{
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return 0;
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}
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int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu)
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{
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struct kvm_cpu_context *cntx;
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struct kvm_vcpu_csr *reset_csr = &vcpu->arch.guest_reset_csr;
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unsigned long host_isa, i;
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/* Mark this VCPU never ran */
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vcpu->arch.ran_atleast_once = false;
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vcpu->arch.mmu_page_cache.gfp_zero = __GFP_ZERO;
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bitmap_zero(vcpu->arch.isa, RISCV_ISA_EXT_MAX);
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/* Setup ISA features available to VCPU */
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for (i = 0; i < ARRAY_SIZE(kvm_isa_ext_arr); i++) {
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host_isa = kvm_isa_ext_arr[i];
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if (__riscv_isa_extension_available(NULL, host_isa) &&
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kvm_riscv_vcpu_isa_enable_allowed(i))
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set_bit(host_isa, vcpu->arch.isa);
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}
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/* Setup vendor, arch, and implementation details */
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vcpu->arch.mvendorid = sbi_get_mvendorid();
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vcpu->arch.marchid = sbi_get_marchid();
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vcpu->arch.mimpid = sbi_get_mimpid();
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/* Setup VCPU hfence queue */
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spin_lock_init(&vcpu->arch.hfence_lock);
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/* Setup reset state of shadow SSTATUS and HSTATUS CSRs */
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cntx = &vcpu->arch.guest_reset_context;
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cntx->sstatus = SR_SPP | SR_SPIE;
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cntx->hstatus = 0;
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cntx->hstatus |= HSTATUS_VTW;
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cntx->hstatus |= HSTATUS_SPVP;
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cntx->hstatus |= HSTATUS_SPV;
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/* By default, make CY, TM, and IR counters accessible in VU mode */
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reset_csr->scounteren = 0x7;
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/* Setup VCPU timer */
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kvm_riscv_vcpu_timer_init(vcpu);
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/* setup performance monitoring */
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kvm_riscv_vcpu_pmu_init(vcpu);
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/* Reset VCPU */
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kvm_riscv_reset_vcpu(vcpu);
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return 0;
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}
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void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
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{
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/**
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* vcpu with id 0 is the designated boot cpu.
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* Keep all vcpus with non-zero id in power-off state so that
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* they can be brought up using SBI HSM extension.
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*/
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if (vcpu->vcpu_idx != 0)
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kvm_riscv_vcpu_power_off(vcpu);
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}
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void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
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{
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/* Cleanup VCPU timer */
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kvm_riscv_vcpu_timer_deinit(vcpu);
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kvm_riscv_vcpu_pmu_deinit(vcpu);
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/* Free unused pages pre-allocated for G-stage page table mappings */
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kvm_mmu_free_memory_cache(&vcpu->arch.mmu_page_cache);
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}
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int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu)
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{
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return kvm_riscv_vcpu_timer_pending(vcpu);
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}
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void kvm_arch_vcpu_blocking(struct kvm_vcpu *vcpu)
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{
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}
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void kvm_arch_vcpu_unblocking(struct kvm_vcpu *vcpu)
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{
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}
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int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
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{
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return (kvm_riscv_vcpu_has_interrupts(vcpu, -1UL) &&
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!vcpu->arch.power_off && !vcpu->arch.pause);
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}
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int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
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{
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return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
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}
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bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
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{
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return (vcpu->arch.guest_context.sstatus & SR_SPP) ? true : false;
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}
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vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
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{
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return VM_FAULT_SIGBUS;
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}
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static int kvm_riscv_vcpu_get_reg_config(struct kvm_vcpu *vcpu,
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const struct kvm_one_reg *reg)
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{
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unsigned long __user *uaddr =
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(unsigned long __user *)(unsigned long)reg->addr;
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unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |
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KVM_REG_SIZE_MASK |
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KVM_REG_RISCV_CONFIG);
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unsigned long reg_val;
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if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long))
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return -EINVAL;
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switch (reg_num) {
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case KVM_REG_RISCV_CONFIG_REG(isa):
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reg_val = vcpu->arch.isa[0] & KVM_RISCV_BASE_ISA_MASK;
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break;
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case KVM_REG_RISCV_CONFIG_REG(zicbom_block_size):
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if (!riscv_isa_extension_available(vcpu->arch.isa, ZICBOM))
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return -EINVAL;
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reg_val = riscv_cbom_block_size;
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break;
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case KVM_REG_RISCV_CONFIG_REG(mvendorid):
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reg_val = vcpu->arch.mvendorid;
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break;
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case KVM_REG_RISCV_CONFIG_REG(marchid):
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reg_val = vcpu->arch.marchid;
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break;
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case KVM_REG_RISCV_CONFIG_REG(mimpid):
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reg_val = vcpu->arch.mimpid;
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break;
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default:
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return -EINVAL;
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}
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if (copy_to_user(uaddr, ®_val, KVM_REG_SIZE(reg->id)))
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return -EFAULT;
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return 0;
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}
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static int kvm_riscv_vcpu_set_reg_config(struct kvm_vcpu *vcpu,
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const struct kvm_one_reg *reg)
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{
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unsigned long __user *uaddr =
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(unsigned long __user *)(unsigned long)reg->addr;
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unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |
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KVM_REG_SIZE_MASK |
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KVM_REG_RISCV_CONFIG);
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unsigned long i, isa_ext, reg_val;
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if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long))
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return -EINVAL;
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if (copy_from_user(®_val, uaddr, KVM_REG_SIZE(reg->id)))
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return -EFAULT;
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switch (reg_num) {
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case KVM_REG_RISCV_CONFIG_REG(isa):
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/*
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* This ONE REG interface is only defined for
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* single letter extensions.
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*/
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if (fls(reg_val) >= RISCV_ISA_EXT_BASE)
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return -EINVAL;
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if (!vcpu->arch.ran_atleast_once) {
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/* Ignore the enable/disable request for certain extensions */
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for (i = 0; i < RISCV_ISA_EXT_BASE; i++) {
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isa_ext = kvm_riscv_vcpu_base2isa_ext(i);
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if (isa_ext >= KVM_RISCV_ISA_EXT_MAX) {
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reg_val &= ~BIT(i);
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continue;
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}
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if (!kvm_riscv_vcpu_isa_enable_allowed(isa_ext))
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if (reg_val & BIT(i))
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reg_val &= ~BIT(i);
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if (!kvm_riscv_vcpu_isa_disable_allowed(isa_ext))
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if (!(reg_val & BIT(i)))
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reg_val |= BIT(i);
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}
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reg_val &= riscv_isa_extension_base(NULL);
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/* Do not modify anything beyond single letter extensions */
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reg_val = (vcpu->arch.isa[0] & ~KVM_RISCV_BASE_ISA_MASK) |
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(reg_val & KVM_RISCV_BASE_ISA_MASK);
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vcpu->arch.isa[0] = reg_val;
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kvm_riscv_vcpu_fp_reset(vcpu);
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} else {
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return -EOPNOTSUPP;
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}
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break;
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case KVM_REG_RISCV_CONFIG_REG(zicbom_block_size):
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return -EOPNOTSUPP;
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case KVM_REG_RISCV_CONFIG_REG(mvendorid):
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if (!vcpu->arch.ran_atleast_once)
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vcpu->arch.mvendorid = reg_val;
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else
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return -EBUSY;
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break;
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case KVM_REG_RISCV_CONFIG_REG(marchid):
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if (!vcpu->arch.ran_atleast_once)
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vcpu->arch.marchid = reg_val;
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else
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return -EBUSY;
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break;
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case KVM_REG_RISCV_CONFIG_REG(mimpid):
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if (!vcpu->arch.ran_atleast_once)
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vcpu->arch.mimpid = reg_val;
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else
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return -EBUSY;
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static int kvm_riscv_vcpu_get_reg_core(struct kvm_vcpu *vcpu,
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const struct kvm_one_reg *reg)
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{
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struct kvm_cpu_context *cntx = &vcpu->arch.guest_context;
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unsigned long __user *uaddr =
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(unsigned long __user *)(unsigned long)reg->addr;
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unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |
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KVM_REG_SIZE_MASK |
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KVM_REG_RISCV_CORE);
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unsigned long reg_val;
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if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long))
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return -EINVAL;
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if (reg_num >= sizeof(struct kvm_riscv_core) / sizeof(unsigned long))
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return -EINVAL;
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if (reg_num == KVM_REG_RISCV_CORE_REG(regs.pc))
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reg_val = cntx->sepc;
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else if (KVM_REG_RISCV_CORE_REG(regs.pc) < reg_num &&
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reg_num <= KVM_REG_RISCV_CORE_REG(regs.t6))
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reg_val = ((unsigned long *)cntx)[reg_num];
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else if (reg_num == KVM_REG_RISCV_CORE_REG(mode))
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reg_val = (cntx->sstatus & SR_SPP) ?
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KVM_RISCV_MODE_S : KVM_RISCV_MODE_U;
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else
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return -EINVAL;
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if (copy_to_user(uaddr, ®_val, KVM_REG_SIZE(reg->id)))
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return -EFAULT;
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return 0;
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}
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static int kvm_riscv_vcpu_set_reg_core(struct kvm_vcpu *vcpu,
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const struct kvm_one_reg *reg)
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{
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struct kvm_cpu_context *cntx = &vcpu->arch.guest_context;
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unsigned long __user *uaddr =
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(unsigned long __user *)(unsigned long)reg->addr;
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unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |
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KVM_REG_SIZE_MASK |
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KVM_REG_RISCV_CORE);
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unsigned long reg_val;
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if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long))
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return -EINVAL;
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if (reg_num >= sizeof(struct kvm_riscv_core) / sizeof(unsigned long))
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return -EINVAL;
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if (copy_from_user(®_val, uaddr, KVM_REG_SIZE(reg->id)))
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return -EFAULT;
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if (reg_num == KVM_REG_RISCV_CORE_REG(regs.pc))
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cntx->sepc = reg_val;
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else if (KVM_REG_RISCV_CORE_REG(regs.pc) < reg_num &&
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reg_num <= KVM_REG_RISCV_CORE_REG(regs.t6))
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((unsigned long *)cntx)[reg_num] = reg_val;
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else if (reg_num == KVM_REG_RISCV_CORE_REG(mode)) {
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if (reg_val == KVM_RISCV_MODE_S)
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cntx->sstatus |= SR_SPP;
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else
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cntx->sstatus &= ~SR_SPP;
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} else
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return -EINVAL;
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return 0;
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}
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static int kvm_riscv_vcpu_get_reg_csr(struct kvm_vcpu *vcpu,
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const struct kvm_one_reg *reg)
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{
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struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr;
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unsigned long __user *uaddr =
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(unsigned long __user *)(unsigned long)reg->addr;
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unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |
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KVM_REG_SIZE_MASK |
|
|
KVM_REG_RISCV_CSR);
|
|
unsigned long reg_val;
|
|
|
|
if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long))
|
|
return -EINVAL;
|
|
if (reg_num >= sizeof(struct kvm_riscv_csr) / sizeof(unsigned long))
|
|
return -EINVAL;
|
|
|
|
if (reg_num == KVM_REG_RISCV_CSR_REG(sip)) {
|
|
kvm_riscv_vcpu_flush_interrupts(vcpu);
|
|
reg_val = (csr->hvip >> VSIP_TO_HVIP_SHIFT) & VSIP_VALID_MASK;
|
|
} else
|
|
reg_val = ((unsigned long *)csr)[reg_num];
|
|
|
|
if (copy_to_user(uaddr, ®_val, KVM_REG_SIZE(reg->id)))
|
|
return -EFAULT;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int kvm_riscv_vcpu_set_reg_csr(struct kvm_vcpu *vcpu,
|
|
const struct kvm_one_reg *reg)
|
|
{
|
|
struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr;
|
|
unsigned long __user *uaddr =
|
|
(unsigned long __user *)(unsigned long)reg->addr;
|
|
unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |
|
|
KVM_REG_SIZE_MASK |
|
|
KVM_REG_RISCV_CSR);
|
|
unsigned long reg_val;
|
|
|
|
if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long))
|
|
return -EINVAL;
|
|
if (reg_num >= sizeof(struct kvm_riscv_csr) / sizeof(unsigned long))
|
|
return -EINVAL;
|
|
|
|
if (copy_from_user(®_val, uaddr, KVM_REG_SIZE(reg->id)))
|
|
return -EFAULT;
|
|
|
|
if (reg_num == KVM_REG_RISCV_CSR_REG(sip)) {
|
|
reg_val &= VSIP_VALID_MASK;
|
|
reg_val <<= VSIP_TO_HVIP_SHIFT;
|
|
}
|
|
|
|
((unsigned long *)csr)[reg_num] = reg_val;
|
|
|
|
if (reg_num == KVM_REG_RISCV_CSR_REG(sip))
|
|
WRITE_ONCE(vcpu->arch.irqs_pending_mask, 0);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int kvm_riscv_vcpu_get_reg_isa_ext(struct kvm_vcpu *vcpu,
|
|
const struct kvm_one_reg *reg)
|
|
{
|
|
unsigned long __user *uaddr =
|
|
(unsigned long __user *)(unsigned long)reg->addr;
|
|
unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |
|
|
KVM_REG_SIZE_MASK |
|
|
KVM_REG_RISCV_ISA_EXT);
|
|
unsigned long reg_val = 0;
|
|
unsigned long host_isa_ext;
|
|
|
|
if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long))
|
|
return -EINVAL;
|
|
|
|
if (reg_num >= KVM_RISCV_ISA_EXT_MAX ||
|
|
reg_num >= ARRAY_SIZE(kvm_isa_ext_arr))
|
|
return -EINVAL;
|
|
|
|
host_isa_ext = kvm_isa_ext_arr[reg_num];
|
|
if (__riscv_isa_extension_available(vcpu->arch.isa, host_isa_ext))
|
|
reg_val = 1; /* Mark the given extension as available */
|
|
|
|
if (copy_to_user(uaddr, ®_val, KVM_REG_SIZE(reg->id)))
|
|
return -EFAULT;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int kvm_riscv_vcpu_set_reg_isa_ext(struct kvm_vcpu *vcpu,
|
|
const struct kvm_one_reg *reg)
|
|
{
|
|
unsigned long __user *uaddr =
|
|
(unsigned long __user *)(unsigned long)reg->addr;
|
|
unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |
|
|
KVM_REG_SIZE_MASK |
|
|
KVM_REG_RISCV_ISA_EXT);
|
|
unsigned long reg_val;
|
|
unsigned long host_isa_ext;
|
|
|
|
if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long))
|
|
return -EINVAL;
|
|
|
|
if (reg_num >= KVM_RISCV_ISA_EXT_MAX ||
|
|
reg_num >= ARRAY_SIZE(kvm_isa_ext_arr))
|
|
return -EINVAL;
|
|
|
|
if (copy_from_user(®_val, uaddr, KVM_REG_SIZE(reg->id)))
|
|
return -EFAULT;
|
|
|
|
host_isa_ext = kvm_isa_ext_arr[reg_num];
|
|
if (!__riscv_isa_extension_available(NULL, host_isa_ext))
|
|
return -EOPNOTSUPP;
|
|
|
|
if (!vcpu->arch.ran_atleast_once) {
|
|
/*
|
|
* All multi-letter extension and a few single letter
|
|
* extension can be disabled
|
|
*/
|
|
if (reg_val == 1 &&
|
|
kvm_riscv_vcpu_isa_enable_allowed(reg_num))
|
|
set_bit(host_isa_ext, vcpu->arch.isa);
|
|
else if (!reg_val &&
|
|
kvm_riscv_vcpu_isa_disable_allowed(reg_num))
|
|
clear_bit(host_isa_ext, vcpu->arch.isa);
|
|
else
|
|
return -EINVAL;
|
|
kvm_riscv_vcpu_fp_reset(vcpu);
|
|
} else {
|
|
return -EOPNOTSUPP;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int kvm_riscv_vcpu_set_reg(struct kvm_vcpu *vcpu,
|
|
const struct kvm_one_reg *reg)
|
|
{
|
|
switch (reg->id & KVM_REG_RISCV_TYPE_MASK) {
|
|
case KVM_REG_RISCV_CONFIG:
|
|
return kvm_riscv_vcpu_set_reg_config(vcpu, reg);
|
|
case KVM_REG_RISCV_CORE:
|
|
return kvm_riscv_vcpu_set_reg_core(vcpu, reg);
|
|
case KVM_REG_RISCV_CSR:
|
|
return kvm_riscv_vcpu_set_reg_csr(vcpu, reg);
|
|
case KVM_REG_RISCV_TIMER:
|
|
return kvm_riscv_vcpu_set_reg_timer(vcpu, reg);
|
|
case KVM_REG_RISCV_FP_F:
|
|
return kvm_riscv_vcpu_set_reg_fp(vcpu, reg,
|
|
KVM_REG_RISCV_FP_F);
|
|
case KVM_REG_RISCV_FP_D:
|
|
return kvm_riscv_vcpu_set_reg_fp(vcpu, reg,
|
|
KVM_REG_RISCV_FP_D);
|
|
case KVM_REG_RISCV_ISA_EXT:
|
|
return kvm_riscv_vcpu_set_reg_isa_ext(vcpu, reg);
|
|
default:
|
|
break;
|
|
}
|
|
|
|
return -EINVAL;
|
|
}
|
|
|
|
static int kvm_riscv_vcpu_get_reg(struct kvm_vcpu *vcpu,
|
|
const struct kvm_one_reg *reg)
|
|
{
|
|
switch (reg->id & KVM_REG_RISCV_TYPE_MASK) {
|
|
case KVM_REG_RISCV_CONFIG:
|
|
return kvm_riscv_vcpu_get_reg_config(vcpu, reg);
|
|
case KVM_REG_RISCV_CORE:
|
|
return kvm_riscv_vcpu_get_reg_core(vcpu, reg);
|
|
case KVM_REG_RISCV_CSR:
|
|
return kvm_riscv_vcpu_get_reg_csr(vcpu, reg);
|
|
case KVM_REG_RISCV_TIMER:
|
|
return kvm_riscv_vcpu_get_reg_timer(vcpu, reg);
|
|
case KVM_REG_RISCV_FP_F:
|
|
return kvm_riscv_vcpu_get_reg_fp(vcpu, reg,
|
|
KVM_REG_RISCV_FP_F);
|
|
case KVM_REG_RISCV_FP_D:
|
|
return kvm_riscv_vcpu_get_reg_fp(vcpu, reg,
|
|
KVM_REG_RISCV_FP_D);
|
|
case KVM_REG_RISCV_ISA_EXT:
|
|
return kvm_riscv_vcpu_get_reg_isa_ext(vcpu, reg);
|
|
default:
|
|
break;
|
|
}
|
|
|
|
return -EINVAL;
|
|
}
|
|
|
|
long kvm_arch_vcpu_async_ioctl(struct file *filp,
|
|
unsigned int ioctl, unsigned long arg)
|
|
{
|
|
struct kvm_vcpu *vcpu = filp->private_data;
|
|
void __user *argp = (void __user *)arg;
|
|
|
|
if (ioctl == KVM_INTERRUPT) {
|
|
struct kvm_interrupt irq;
|
|
|
|
if (copy_from_user(&irq, argp, sizeof(irq)))
|
|
return -EFAULT;
|
|
|
|
if (irq.irq == KVM_INTERRUPT_SET)
|
|
return kvm_riscv_vcpu_set_interrupt(vcpu, IRQ_VS_EXT);
|
|
else
|
|
return kvm_riscv_vcpu_unset_interrupt(vcpu, IRQ_VS_EXT);
|
|
}
|
|
|
|
return -ENOIOCTLCMD;
|
|
}
|
|
|
|
long kvm_arch_vcpu_ioctl(struct file *filp,
|
|
unsigned int ioctl, unsigned long arg)
|
|
{
|
|
struct kvm_vcpu *vcpu = filp->private_data;
|
|
void __user *argp = (void __user *)arg;
|
|
long r = -EINVAL;
|
|
|
|
switch (ioctl) {
|
|
case KVM_SET_ONE_REG:
|
|
case KVM_GET_ONE_REG: {
|
|
struct kvm_one_reg reg;
|
|
|
|
r = -EFAULT;
|
|
if (copy_from_user(®, argp, sizeof(reg)))
|
|
break;
|
|
|
|
if (ioctl == KVM_SET_ONE_REG)
|
|
r = kvm_riscv_vcpu_set_reg(vcpu, ®);
|
|
else
|
|
r = kvm_riscv_vcpu_get_reg(vcpu, ®);
|
|
break;
|
|
}
|
|
default:
|
|
break;
|
|
}
|
|
|
|
return r;
|
|
}
|
|
|
|
int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
|
|
struct kvm_sregs *sregs)
|
|
{
|
|
return -EINVAL;
|
|
}
|
|
|
|
int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
|
|
struct kvm_sregs *sregs)
|
|
{
|
|
return -EINVAL;
|
|
}
|
|
|
|
int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
|
|
{
|
|
return -EINVAL;
|
|
}
|
|
|
|
int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
|
|
{
|
|
return -EINVAL;
|
|
}
|
|
|
|
int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
|
|
struct kvm_translation *tr)
|
|
{
|
|
return -EINVAL;
|
|
}
|
|
|
|
int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
|
|
{
|
|
return -EINVAL;
|
|
}
|
|
|
|
int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
|
|
{
|
|
return -EINVAL;
|
|
}
|
|
|
|
void kvm_riscv_vcpu_flush_interrupts(struct kvm_vcpu *vcpu)
|
|
{
|
|
struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr;
|
|
unsigned long mask, val;
|
|
|
|
if (READ_ONCE(vcpu->arch.irqs_pending_mask)) {
|
|
mask = xchg_acquire(&vcpu->arch.irqs_pending_mask, 0);
|
|
val = READ_ONCE(vcpu->arch.irqs_pending) & mask;
|
|
|
|
csr->hvip &= ~mask;
|
|
csr->hvip |= val;
|
|
}
|
|
}
|
|
|
|
void kvm_riscv_vcpu_sync_interrupts(struct kvm_vcpu *vcpu)
|
|
{
|
|
unsigned long hvip;
|
|
struct kvm_vcpu_arch *v = &vcpu->arch;
|
|
struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr;
|
|
|
|
/* Read current HVIP and VSIE CSRs */
|
|
csr->vsie = csr_read(CSR_VSIE);
|
|
|
|
/* Sync-up HVIP.VSSIP bit changes does by Guest */
|
|
hvip = csr_read(CSR_HVIP);
|
|
if ((csr->hvip ^ hvip) & (1UL << IRQ_VS_SOFT)) {
|
|
if (hvip & (1UL << IRQ_VS_SOFT)) {
|
|
if (!test_and_set_bit(IRQ_VS_SOFT,
|
|
&v->irqs_pending_mask))
|
|
set_bit(IRQ_VS_SOFT, &v->irqs_pending);
|
|
} else {
|
|
if (!test_and_set_bit(IRQ_VS_SOFT,
|
|
&v->irqs_pending_mask))
|
|
clear_bit(IRQ_VS_SOFT, &v->irqs_pending);
|
|
}
|
|
}
|
|
|
|
/* Sync-up timer CSRs */
|
|
kvm_riscv_vcpu_timer_sync(vcpu);
|
|
}
|
|
|
|
int kvm_riscv_vcpu_set_interrupt(struct kvm_vcpu *vcpu, unsigned int irq)
|
|
{
|
|
if (irq != IRQ_VS_SOFT &&
|
|
irq != IRQ_VS_TIMER &&
|
|
irq != IRQ_VS_EXT)
|
|
return -EINVAL;
|
|
|
|
set_bit(irq, &vcpu->arch.irqs_pending);
|
|
smp_mb__before_atomic();
|
|
set_bit(irq, &vcpu->arch.irqs_pending_mask);
|
|
|
|
kvm_vcpu_kick(vcpu);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int kvm_riscv_vcpu_unset_interrupt(struct kvm_vcpu *vcpu, unsigned int irq)
|
|
{
|
|
if (irq != IRQ_VS_SOFT &&
|
|
irq != IRQ_VS_TIMER &&
|
|
irq != IRQ_VS_EXT)
|
|
return -EINVAL;
|
|
|
|
clear_bit(irq, &vcpu->arch.irqs_pending);
|
|
smp_mb__before_atomic();
|
|
set_bit(irq, &vcpu->arch.irqs_pending_mask);
|
|
|
|
return 0;
|
|
}
|
|
|
|
bool kvm_riscv_vcpu_has_interrupts(struct kvm_vcpu *vcpu, unsigned long mask)
|
|
{
|
|
unsigned long ie = ((vcpu->arch.guest_csr.vsie & VSIP_VALID_MASK)
|
|
<< VSIP_TO_HVIP_SHIFT) & mask;
|
|
|
|
return (READ_ONCE(vcpu->arch.irqs_pending) & ie) ? true : false;
|
|
}
|
|
|
|
void kvm_riscv_vcpu_power_off(struct kvm_vcpu *vcpu)
|
|
{
|
|
vcpu->arch.power_off = true;
|
|
kvm_make_request(KVM_REQ_SLEEP, vcpu);
|
|
kvm_vcpu_kick(vcpu);
|
|
}
|
|
|
|
void kvm_riscv_vcpu_power_on(struct kvm_vcpu *vcpu)
|
|
{
|
|
vcpu->arch.power_off = false;
|
|
kvm_vcpu_wake_up(vcpu);
|
|
}
|
|
|
|
int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
|
|
struct kvm_mp_state *mp_state)
|
|
{
|
|
if (vcpu->arch.power_off)
|
|
mp_state->mp_state = KVM_MP_STATE_STOPPED;
|
|
else
|
|
mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
|
|
|
|
return 0;
|
|
}
|
|
|
|
int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
|
|
struct kvm_mp_state *mp_state)
|
|
{
|
|
int ret = 0;
|
|
|
|
switch (mp_state->mp_state) {
|
|
case KVM_MP_STATE_RUNNABLE:
|
|
vcpu->arch.power_off = false;
|
|
break;
|
|
case KVM_MP_STATE_STOPPED:
|
|
kvm_riscv_vcpu_power_off(vcpu);
|
|
break;
|
|
default:
|
|
ret = -EINVAL;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
|
|
struct kvm_guest_debug *dbg)
|
|
{
|
|
/* TODO; To be implemented later. */
|
|
return -EINVAL;
|
|
}
|
|
|
|
static void kvm_riscv_vcpu_update_config(const unsigned long *isa)
|
|
{
|
|
u64 henvcfg = 0;
|
|
|
|
if (riscv_isa_extension_available(isa, SVPBMT))
|
|
henvcfg |= ENVCFG_PBMTE;
|
|
|
|
if (riscv_isa_extension_available(isa, SSTC))
|
|
henvcfg |= ENVCFG_STCE;
|
|
|
|
if (riscv_isa_extension_available(isa, ZICBOM))
|
|
henvcfg |= (ENVCFG_CBIE | ENVCFG_CBCFE);
|
|
|
|
csr_write(CSR_HENVCFG, henvcfg);
|
|
#ifdef CONFIG_32BIT
|
|
csr_write(CSR_HENVCFGH, henvcfg >> 32);
|
|
#endif
|
|
}
|
|
|
|
void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
|
|
{
|
|
struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr;
|
|
|
|
csr_write(CSR_VSSTATUS, csr->vsstatus);
|
|
csr_write(CSR_VSIE, csr->vsie);
|
|
csr_write(CSR_VSTVEC, csr->vstvec);
|
|
csr_write(CSR_VSSCRATCH, csr->vsscratch);
|
|
csr_write(CSR_VSEPC, csr->vsepc);
|
|
csr_write(CSR_VSCAUSE, csr->vscause);
|
|
csr_write(CSR_VSTVAL, csr->vstval);
|
|
csr_write(CSR_HVIP, csr->hvip);
|
|
csr_write(CSR_VSATP, csr->vsatp);
|
|
|
|
kvm_riscv_vcpu_update_config(vcpu->arch.isa);
|
|
|
|
kvm_riscv_gstage_update_hgatp(vcpu);
|
|
|
|
kvm_riscv_vcpu_timer_restore(vcpu);
|
|
|
|
kvm_riscv_vcpu_host_fp_save(&vcpu->arch.host_context);
|
|
kvm_riscv_vcpu_guest_fp_restore(&vcpu->arch.guest_context,
|
|
vcpu->arch.isa);
|
|
|
|
vcpu->cpu = cpu;
|
|
}
|
|
|
|
void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
|
|
{
|
|
struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr;
|
|
|
|
vcpu->cpu = -1;
|
|
|
|
kvm_riscv_vcpu_guest_fp_save(&vcpu->arch.guest_context,
|
|
vcpu->arch.isa);
|
|
kvm_riscv_vcpu_host_fp_restore(&vcpu->arch.host_context);
|
|
|
|
kvm_riscv_vcpu_timer_save(vcpu);
|
|
|
|
csr->vsstatus = csr_read(CSR_VSSTATUS);
|
|
csr->vsie = csr_read(CSR_VSIE);
|
|
csr->vstvec = csr_read(CSR_VSTVEC);
|
|
csr->vsscratch = csr_read(CSR_VSSCRATCH);
|
|
csr->vsepc = csr_read(CSR_VSEPC);
|
|
csr->vscause = csr_read(CSR_VSCAUSE);
|
|
csr->vstval = csr_read(CSR_VSTVAL);
|
|
csr->hvip = csr_read(CSR_HVIP);
|
|
csr->vsatp = csr_read(CSR_VSATP);
|
|
}
|
|
|
|
static void kvm_riscv_check_vcpu_requests(struct kvm_vcpu *vcpu)
|
|
{
|
|
struct rcuwait *wait = kvm_arch_vcpu_get_wait(vcpu);
|
|
|
|
if (kvm_request_pending(vcpu)) {
|
|
if (kvm_check_request(KVM_REQ_SLEEP, vcpu)) {
|
|
kvm_vcpu_srcu_read_unlock(vcpu);
|
|
rcuwait_wait_event(wait,
|
|
(!vcpu->arch.power_off) && (!vcpu->arch.pause),
|
|
TASK_INTERRUPTIBLE);
|
|
kvm_vcpu_srcu_read_lock(vcpu);
|
|
|
|
if (vcpu->arch.power_off || vcpu->arch.pause) {
|
|
/*
|
|
* Awaken to handle a signal, request to
|
|
* sleep again later.
|
|
*/
|
|
kvm_make_request(KVM_REQ_SLEEP, vcpu);
|
|
}
|
|
}
|
|
|
|
if (kvm_check_request(KVM_REQ_VCPU_RESET, vcpu))
|
|
kvm_riscv_reset_vcpu(vcpu);
|
|
|
|
if (kvm_check_request(KVM_REQ_UPDATE_HGATP, vcpu))
|
|
kvm_riscv_gstage_update_hgatp(vcpu);
|
|
|
|
if (kvm_check_request(KVM_REQ_FENCE_I, vcpu))
|
|
kvm_riscv_fence_i_process(vcpu);
|
|
|
|
/*
|
|
* The generic KVM_REQ_TLB_FLUSH is same as
|
|
* KVM_REQ_HFENCE_GVMA_VMID_ALL
|
|
*/
|
|
if (kvm_check_request(KVM_REQ_HFENCE_GVMA_VMID_ALL, vcpu))
|
|
kvm_riscv_hfence_gvma_vmid_all_process(vcpu);
|
|
|
|
if (kvm_check_request(KVM_REQ_HFENCE_VVMA_ALL, vcpu))
|
|
kvm_riscv_hfence_vvma_all_process(vcpu);
|
|
|
|
if (kvm_check_request(KVM_REQ_HFENCE, vcpu))
|
|
kvm_riscv_hfence_process(vcpu);
|
|
}
|
|
}
|
|
|
|
static void kvm_riscv_update_hvip(struct kvm_vcpu *vcpu)
|
|
{
|
|
struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr;
|
|
|
|
csr_write(CSR_HVIP, csr->hvip);
|
|
}
|
|
|
|
/*
|
|
* Actually run the vCPU, entering an RCU extended quiescent state (EQS) while
|
|
* the vCPU is running.
|
|
*
|
|
* This must be noinstr as instrumentation may make use of RCU, and this is not
|
|
* safe during the EQS.
|
|
*/
|
|
static void noinstr kvm_riscv_vcpu_enter_exit(struct kvm_vcpu *vcpu)
|
|
{
|
|
guest_state_enter_irqoff();
|
|
__kvm_riscv_switch_to(&vcpu->arch);
|
|
vcpu->arch.last_exit_cpu = vcpu->cpu;
|
|
guest_state_exit_irqoff();
|
|
}
|
|
|
|
int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu)
|
|
{
|
|
int ret;
|
|
struct kvm_cpu_trap trap;
|
|
struct kvm_run *run = vcpu->run;
|
|
|
|
/* Mark this VCPU ran at least once */
|
|
vcpu->arch.ran_atleast_once = true;
|
|
|
|
kvm_vcpu_srcu_read_lock(vcpu);
|
|
|
|
switch (run->exit_reason) {
|
|
case KVM_EXIT_MMIO:
|
|
/* Process MMIO value returned from user-space */
|
|
ret = kvm_riscv_vcpu_mmio_return(vcpu, vcpu->run);
|
|
break;
|
|
case KVM_EXIT_RISCV_SBI:
|
|
/* Process SBI value returned from user-space */
|
|
ret = kvm_riscv_vcpu_sbi_return(vcpu, vcpu->run);
|
|
break;
|
|
case KVM_EXIT_RISCV_CSR:
|
|
/* Process CSR value returned from user-space */
|
|
ret = kvm_riscv_vcpu_csr_return(vcpu, vcpu->run);
|
|
break;
|
|
default:
|
|
ret = 0;
|
|
break;
|
|
}
|
|
if (ret) {
|
|
kvm_vcpu_srcu_read_unlock(vcpu);
|
|
return ret;
|
|
}
|
|
|
|
if (run->immediate_exit) {
|
|
kvm_vcpu_srcu_read_unlock(vcpu);
|
|
return -EINTR;
|
|
}
|
|
|
|
vcpu_load(vcpu);
|
|
|
|
kvm_sigset_activate(vcpu);
|
|
|
|
ret = 1;
|
|
run->exit_reason = KVM_EXIT_UNKNOWN;
|
|
while (ret > 0) {
|
|
/* Check conditions before entering the guest */
|
|
ret = xfer_to_guest_mode_handle_work(vcpu);
|
|
if (ret)
|
|
continue;
|
|
ret = 1;
|
|
|
|
kvm_riscv_gstage_vmid_update(vcpu);
|
|
|
|
kvm_riscv_check_vcpu_requests(vcpu);
|
|
|
|
local_irq_disable();
|
|
|
|
/*
|
|
* Ensure we set mode to IN_GUEST_MODE after we disable
|
|
* interrupts and before the final VCPU requests check.
|
|
* See the comment in kvm_vcpu_exiting_guest_mode() and
|
|
* Documentation/virt/kvm/vcpu-requests.rst
|
|
*/
|
|
vcpu->mode = IN_GUEST_MODE;
|
|
|
|
kvm_vcpu_srcu_read_unlock(vcpu);
|
|
smp_mb__after_srcu_read_unlock();
|
|
|
|
/*
|
|
* We might have got VCPU interrupts updated asynchronously
|
|
* so update it in HW.
|
|
*/
|
|
kvm_riscv_vcpu_flush_interrupts(vcpu);
|
|
|
|
/* Update HVIP CSR for current CPU */
|
|
kvm_riscv_update_hvip(vcpu);
|
|
|
|
if (ret <= 0 ||
|
|
kvm_riscv_gstage_vmid_ver_changed(&vcpu->kvm->arch.vmid) ||
|
|
kvm_request_pending(vcpu) ||
|
|
xfer_to_guest_mode_work_pending()) {
|
|
vcpu->mode = OUTSIDE_GUEST_MODE;
|
|
local_irq_enable();
|
|
kvm_vcpu_srcu_read_lock(vcpu);
|
|
continue;
|
|
}
|
|
|
|
/*
|
|
* Cleanup stale TLB enteries
|
|
*
|
|
* Note: This should be done after G-stage VMID has been
|
|
* updated using kvm_riscv_gstage_vmid_ver_changed()
|
|
*/
|
|
kvm_riscv_local_tlb_sanitize(vcpu);
|
|
|
|
guest_timing_enter_irqoff();
|
|
|
|
kvm_riscv_vcpu_enter_exit(vcpu);
|
|
|
|
vcpu->mode = OUTSIDE_GUEST_MODE;
|
|
vcpu->stat.exits++;
|
|
|
|
/*
|
|
* Save SCAUSE, STVAL, HTVAL, and HTINST because we might
|
|
* get an interrupt between __kvm_riscv_switch_to() and
|
|
* local_irq_enable() which can potentially change CSRs.
|
|
*/
|
|
trap.sepc = vcpu->arch.guest_context.sepc;
|
|
trap.scause = csr_read(CSR_SCAUSE);
|
|
trap.stval = csr_read(CSR_STVAL);
|
|
trap.htval = csr_read(CSR_HTVAL);
|
|
trap.htinst = csr_read(CSR_HTINST);
|
|
|
|
/* Syncup interrupts state with HW */
|
|
kvm_riscv_vcpu_sync_interrupts(vcpu);
|
|
|
|
preempt_disable();
|
|
|
|
/*
|
|
* We must ensure that any pending interrupts are taken before
|
|
* we exit guest timing so that timer ticks are accounted as
|
|
* guest time. Transiently unmask interrupts so that any
|
|
* pending interrupts are taken.
|
|
*
|
|
* There's no barrier which ensures that pending interrupts are
|
|
* recognised, so we just hope that the CPU takes any pending
|
|
* interrupts between the enable and disable.
|
|
*/
|
|
local_irq_enable();
|
|
local_irq_disable();
|
|
|
|
guest_timing_exit_irqoff();
|
|
|
|
local_irq_enable();
|
|
|
|
preempt_enable();
|
|
|
|
kvm_vcpu_srcu_read_lock(vcpu);
|
|
|
|
ret = kvm_riscv_vcpu_exit(vcpu, run, &trap);
|
|
}
|
|
|
|
kvm_sigset_deactivate(vcpu);
|
|
|
|
vcpu_put(vcpu);
|
|
|
|
kvm_vcpu_srcu_read_unlock(vcpu);
|
|
|
|
return ret;
|
|
}
|