274 lines
7.8 KiB
ArmAsm
274 lines
7.8 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Hardware-accelerated CRC-32 variants for Linux on z Systems
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*
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* Use the z/Architecture Vector Extension Facility to accelerate the
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* computing of bitreflected CRC-32 checksums for IEEE 802.3 Ethernet
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* and Castagnoli.
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*
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* This CRC-32 implementation algorithm is bitreflected and processes
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* the least-significant bit first (Little-Endian).
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*
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* Copyright IBM Corp. 2015
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* Author(s): Hendrik Brueckner <brueckner@linux.vnet.ibm.com>
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*/
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#include <linux/linkage.h>
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#include <asm/nospec-insn.h>
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#include <asm/vx-insn.h>
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/* Vector register range containing CRC-32 constants */
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#define CONST_PERM_LE2BE %v9
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#define CONST_R2R1 %v10
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#define CONST_R4R3 %v11
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#define CONST_R5 %v12
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#define CONST_RU_POLY %v13
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#define CONST_CRC_POLY %v14
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.data
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.align 8
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/*
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* The CRC-32 constant block contains reduction constants to fold and
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* process particular chunks of the input data stream in parallel.
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*
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* For the CRC-32 variants, the constants are precomputed according to
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* these definitions:
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*
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* R1 = [(x4*128+32 mod P'(x) << 32)]' << 1
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* R2 = [(x4*128-32 mod P'(x) << 32)]' << 1
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* R3 = [(x128+32 mod P'(x) << 32)]' << 1
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* R4 = [(x128-32 mod P'(x) << 32)]' << 1
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* R5 = [(x64 mod P'(x) << 32)]' << 1
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* R6 = [(x32 mod P'(x) << 32)]' << 1
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*
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* The bitreflected Barret reduction constant, u', is defined as
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* the bit reversal of floor(x**64 / P(x)).
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*
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* where P(x) is the polynomial in the normal domain and the P'(x) is the
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* polynomial in the reversed (bitreflected) domain.
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*
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* CRC-32 (IEEE 802.3 Ethernet, ...) polynomials:
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*
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* P(x) = 0x04C11DB7
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* P'(x) = 0xEDB88320
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*
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* CRC-32C (Castagnoli) polynomials:
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*
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* P(x) = 0x1EDC6F41
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* P'(x) = 0x82F63B78
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*/
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.Lconstants_CRC_32_LE:
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.octa 0x0F0E0D0C0B0A09080706050403020100 # BE->LE mask
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.quad 0x1c6e41596, 0x154442bd4 # R2, R1
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.quad 0x0ccaa009e, 0x1751997d0 # R4, R3
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.octa 0x163cd6124 # R5
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.octa 0x1F7011641 # u'
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.octa 0x1DB710641 # P'(x) << 1
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.Lconstants_CRC_32C_LE:
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.octa 0x0F0E0D0C0B0A09080706050403020100 # BE->LE mask
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.quad 0x09e4addf8, 0x740eef02 # R2, R1
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.quad 0x14cd00bd6, 0xf20c0dfe # R4, R3
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.octa 0x0dd45aab8 # R5
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.octa 0x0dea713f1 # u'
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.octa 0x105ec76f0 # P'(x) << 1
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.previous
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GEN_BR_THUNK %r14
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.text
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/*
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* The CRC-32 functions use these calling conventions:
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*
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* Parameters:
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*
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* %r2: Initial CRC value, typically ~0; and final CRC (return) value.
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* %r3: Input buffer pointer, performance might be improved if the
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* buffer is on a doubleword boundary.
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* %r4: Length of the buffer, must be 64 bytes or greater.
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*
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* Register usage:
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*
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* %r5: CRC-32 constant pool base pointer.
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* V0: Initial CRC value and intermediate constants and results.
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* V1..V4: Data for CRC computation.
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* V5..V8: Next data chunks that are fetched from the input buffer.
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* V9: Constant for BE->LE conversion and shift operations
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*
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* V10..V14: CRC-32 constants.
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*/
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ENTRY(crc32_le_vgfm_16)
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larl %r5,.Lconstants_CRC_32_LE
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j crc32_le_vgfm_generic
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ENDPROC(crc32_le_vgfm_16)
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ENTRY(crc32c_le_vgfm_16)
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larl %r5,.Lconstants_CRC_32C_LE
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j crc32_le_vgfm_generic
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ENDPROC(crc32c_le_vgfm_16)
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ENTRY(crc32_le_vgfm_generic)
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/* Load CRC-32 constants */
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VLM CONST_PERM_LE2BE,CONST_CRC_POLY,0,%r5
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/*
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* Load the initial CRC value.
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*
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* The CRC value is loaded into the rightmost word of the
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* vector register and is later XORed with the LSB portion
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* of the loaded input data.
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*/
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VZERO %v0 /* Clear V0 */
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VLVGF %v0,%r2,3 /* Load CRC into rightmost word */
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/* Load a 64-byte data chunk and XOR with CRC */
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VLM %v1,%v4,0,%r3 /* 64-bytes into V1..V4 */
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VPERM %v1,%v1,%v1,CONST_PERM_LE2BE
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VPERM %v2,%v2,%v2,CONST_PERM_LE2BE
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VPERM %v3,%v3,%v3,CONST_PERM_LE2BE
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VPERM %v4,%v4,%v4,CONST_PERM_LE2BE
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VX %v1,%v0,%v1 /* V1 ^= CRC */
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aghi %r3,64 /* BUF = BUF + 64 */
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aghi %r4,-64 /* LEN = LEN - 64 */
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cghi %r4,64
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jl .Lless_than_64bytes
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.Lfold_64bytes_loop:
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/* Load the next 64-byte data chunk into V5 to V8 */
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VLM %v5,%v8,0,%r3
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VPERM %v5,%v5,%v5,CONST_PERM_LE2BE
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VPERM %v6,%v6,%v6,CONST_PERM_LE2BE
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VPERM %v7,%v7,%v7,CONST_PERM_LE2BE
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VPERM %v8,%v8,%v8,CONST_PERM_LE2BE
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/*
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* Perform a GF(2) multiplication of the doublewords in V1 with
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* the R1 and R2 reduction constants in V0. The intermediate result
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* is then folded (accumulated) with the next data chunk in V5 and
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* stored in V1. Repeat this step for the register contents
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* in V2, V3, and V4 respectively.
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*/
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VGFMAG %v1,CONST_R2R1,%v1,%v5
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VGFMAG %v2,CONST_R2R1,%v2,%v6
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VGFMAG %v3,CONST_R2R1,%v3,%v7
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VGFMAG %v4,CONST_R2R1,%v4,%v8
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aghi %r3,64 /* BUF = BUF + 64 */
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aghi %r4,-64 /* LEN = LEN - 64 */
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cghi %r4,64
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jnl .Lfold_64bytes_loop
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.Lless_than_64bytes:
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/*
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* Fold V1 to V4 into a single 128-bit value in V1. Multiply V1 with R3
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* and R4 and accumulating the next 128-bit chunk until a single 128-bit
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* value remains.
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*/
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VGFMAG %v1,CONST_R4R3,%v1,%v2
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VGFMAG %v1,CONST_R4R3,%v1,%v3
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VGFMAG %v1,CONST_R4R3,%v1,%v4
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cghi %r4,16
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jl .Lfinal_fold
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.Lfold_16bytes_loop:
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VL %v2,0,,%r3 /* Load next data chunk */
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VPERM %v2,%v2,%v2,CONST_PERM_LE2BE
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VGFMAG %v1,CONST_R4R3,%v1,%v2 /* Fold next data chunk */
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aghi %r3,16
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aghi %r4,-16
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cghi %r4,16
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jnl .Lfold_16bytes_loop
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.Lfinal_fold:
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/*
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* Set up a vector register for byte shifts. The shift value must
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* be loaded in bits 1-4 in byte element 7 of a vector register.
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* Shift by 8 bytes: 0x40
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* Shift by 4 bytes: 0x20
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*/
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VLEIB %v9,0x40,7
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/*
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* Prepare V0 for the next GF(2) multiplication: shift V0 by 8 bytes
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* to move R4 into the rightmost doubleword and set the leftmost
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* doubleword to 0x1.
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*/
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VSRLB %v0,CONST_R4R3,%v9
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VLEIG %v0,1,0
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/*
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* Compute GF(2) product of V1 and V0. The rightmost doubleword
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* of V1 is multiplied with R4. The leftmost doubleword of V1 is
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* multiplied by 0x1 and is then XORed with rightmost product.
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* Implicitly, the intermediate leftmost product becomes padded
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*/
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VGFMG %v1,%v0,%v1
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/*
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* Now do the final 32-bit fold by multiplying the rightmost word
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* in V1 with R5 and XOR the result with the remaining bits in V1.
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*
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* To achieve this by a single VGFMAG, right shift V1 by a word
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* and store the result in V2 which is then accumulated. Use the
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* vector unpack instruction to load the rightmost half of the
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* doubleword into the rightmost doubleword element of V1; the other
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* half is loaded in the leftmost doubleword.
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* The vector register with CONST_R5 contains the R5 constant in the
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* rightmost doubleword and the leftmost doubleword is zero to ignore
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* the leftmost product of V1.
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*/
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VLEIB %v9,0x20,7 /* Shift by words */
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VSRLB %v2,%v1,%v9 /* Store remaining bits in V2 */
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VUPLLF %v1,%v1 /* Split rightmost doubleword */
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VGFMAG %v1,CONST_R5,%v1,%v2 /* V1 = (V1 * R5) XOR V2 */
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/*
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* Apply a Barret reduction to compute the final 32-bit CRC value.
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*
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* The input values to the Barret reduction are the degree-63 polynomial
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* in V1 (R(x)), degree-32 generator polynomial, and the reduction
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* constant u. The Barret reduction result is the CRC value of R(x) mod
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* P(x).
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*
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* The Barret reduction algorithm is defined as:
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*
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* 1. T1(x) = floor( R(x) / x^32 ) GF2MUL u
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* 2. T2(x) = floor( T1(x) / x^32 ) GF2MUL P(x)
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* 3. C(x) = R(x) XOR T2(x) mod x^32
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*
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* Note: The leftmost doubleword of vector register containing
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* CONST_RU_POLY is zero and, thus, the intermediate GF(2) product
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* is zero and does not contribute to the final result.
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*/
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/* T1(x) = floor( R(x) / x^32 ) GF2MUL u */
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VUPLLF %v2,%v1
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VGFMG %v2,CONST_RU_POLY,%v2
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/*
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* Compute the GF(2) product of the CRC polynomial with T1(x) in
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* V2 and XOR the intermediate result, T2(x), with the value in V1.
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* The final result is stored in word element 2 of V2.
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*/
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VUPLLF %v2,%v2
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VGFMAG %v2,CONST_CRC_POLY,%v2,%v1
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.Ldone:
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VLGVF %r2,%v2,2
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BR_EX %r14
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ENDPROC(crc32_le_vgfm_generic)
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.previous
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