310 lines
7.5 KiB
ArmAsm
310 lines
7.5 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Asm versions of Xen pv-ops, suitable for direct use.
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*
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* We only bother with direct forms (ie, vcpu in percpu data) of the
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* operations here; the indirect forms are better handled in C.
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*/
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#include <asm/errno.h>
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#include <asm/asm-offsets.h>
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#include <asm/percpu.h>
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#include <asm/processor-flags.h>
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#include <asm/segment.h>
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#include <asm/thread_info.h>
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#include <asm/asm.h>
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#include <asm/frame.h>
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#include <asm/unwind_hints.h>
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#include <xen/interface/xen.h>
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#include <linux/init.h>
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#include <linux/linkage.h>
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#include <../entry/calling.h>
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.pushsection .noinstr.text, "ax"
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/*
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* Disabling events is simply a matter of making the event mask
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* non-zero.
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*/
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SYM_FUNC_START(xen_irq_disable_direct)
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movb $1, PER_CPU_VAR(xen_vcpu_info) + XEN_vcpu_info_mask
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RET
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SYM_FUNC_END(xen_irq_disable_direct)
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/*
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* Force an event check by making a hypercall, but preserve regs
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* before making the call.
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*/
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SYM_FUNC_START(check_events)
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FRAME_BEGIN
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push %rax
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push %rcx
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push %rdx
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push %rsi
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push %rdi
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push %r8
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push %r9
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push %r10
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push %r11
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call xen_force_evtchn_callback
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pop %r11
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pop %r10
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pop %r9
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pop %r8
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pop %rdi
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pop %rsi
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pop %rdx
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pop %rcx
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pop %rax
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FRAME_END
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RET
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SYM_FUNC_END(check_events)
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/*
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* Enable events. This clears the event mask and tests the pending
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* event status with one and operation. If there are pending events,
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* then enter the hypervisor to get them handled.
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*/
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SYM_FUNC_START(xen_irq_enable_direct)
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FRAME_BEGIN
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/* Unmask events */
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movb $0, PER_CPU_VAR(xen_vcpu_info) + XEN_vcpu_info_mask
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/*
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* Preempt here doesn't matter because that will deal with any
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* pending interrupts. The pending check may end up being run
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* on the wrong CPU, but that doesn't hurt.
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*/
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/* Test for pending */
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testb $0xff, PER_CPU_VAR(xen_vcpu_info) + XEN_vcpu_info_pending
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jz 1f
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call check_events
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1:
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FRAME_END
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RET
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SYM_FUNC_END(xen_irq_enable_direct)
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/*
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* (xen_)save_fl is used to get the current interrupt enable status.
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* Callers expect the status to be in X86_EFLAGS_IF, and other bits
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* may be set in the return value. We take advantage of this by
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* making sure that X86_EFLAGS_IF has the right value (and other bits
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* in that byte are 0), but other bits in the return value are
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* undefined. We need to toggle the state of the bit, because Xen and
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* x86 use opposite senses (mask vs enable).
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*/
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SYM_FUNC_START(xen_save_fl_direct)
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testb $0xff, PER_CPU_VAR(xen_vcpu_info) + XEN_vcpu_info_mask
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setz %ah
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addb %ah, %ah
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RET
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SYM_FUNC_END(xen_save_fl_direct)
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SYM_FUNC_START(xen_read_cr2)
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FRAME_BEGIN
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_ASM_MOV PER_CPU_VAR(xen_vcpu), %_ASM_AX
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_ASM_MOV XEN_vcpu_info_arch_cr2(%_ASM_AX), %_ASM_AX
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FRAME_END
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RET
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SYM_FUNC_END(xen_read_cr2);
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SYM_FUNC_START(xen_read_cr2_direct)
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FRAME_BEGIN
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_ASM_MOV PER_CPU_VAR(xen_vcpu_info) + XEN_vcpu_info_arch_cr2, %_ASM_AX
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FRAME_END
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RET
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SYM_FUNC_END(xen_read_cr2_direct);
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.popsection
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.macro xen_pv_trap name
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SYM_CODE_START(xen_\name)
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UNWIND_HINT_ENTRY
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ENDBR
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pop %rcx
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pop %r11
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jmp \name
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SYM_CODE_END(xen_\name)
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_ASM_NOKPROBE(xen_\name)
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.endm
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xen_pv_trap asm_exc_divide_error
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xen_pv_trap asm_xenpv_exc_debug
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xen_pv_trap asm_exc_int3
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xen_pv_trap asm_xenpv_exc_nmi
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xen_pv_trap asm_exc_overflow
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xen_pv_trap asm_exc_bounds
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xen_pv_trap asm_exc_invalid_op
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xen_pv_trap asm_exc_device_not_available
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xen_pv_trap asm_xenpv_exc_double_fault
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xen_pv_trap asm_exc_coproc_segment_overrun
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xen_pv_trap asm_exc_invalid_tss
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xen_pv_trap asm_exc_segment_not_present
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xen_pv_trap asm_exc_stack_segment
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xen_pv_trap asm_exc_general_protection
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xen_pv_trap asm_exc_page_fault
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xen_pv_trap asm_exc_spurious_interrupt_bug
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xen_pv_trap asm_exc_coprocessor_error
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xen_pv_trap asm_exc_alignment_check
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#ifdef CONFIG_X86_KERNEL_IBT
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xen_pv_trap asm_exc_control_protection
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#endif
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#ifdef CONFIG_X86_MCE
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xen_pv_trap asm_xenpv_exc_machine_check
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#endif /* CONFIG_X86_MCE */
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xen_pv_trap asm_exc_simd_coprocessor_error
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#ifdef CONFIG_IA32_EMULATION
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xen_pv_trap entry_INT80_compat
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#endif
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xen_pv_trap asm_exc_xen_unknown_trap
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xen_pv_trap asm_exc_xen_hypervisor_callback
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__INIT
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SYM_CODE_START(xen_early_idt_handler_array)
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i = 0
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.rept NUM_EXCEPTION_VECTORS
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UNWIND_HINT_EMPTY
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ENDBR
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pop %rcx
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pop %r11
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jmp early_idt_handler_array + i*EARLY_IDT_HANDLER_SIZE
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i = i + 1
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.fill xen_early_idt_handler_array + i*XEN_EARLY_IDT_HANDLER_SIZE - ., 1, 0xcc
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.endr
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SYM_CODE_END(xen_early_idt_handler_array)
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__FINIT
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hypercall_iret = hypercall_page + __HYPERVISOR_iret * 32
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/*
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* Xen64 iret frame:
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*
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* ss
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* rsp
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* rflags
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* cs
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* rip <-- standard iret frame
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*
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* flags
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*
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* rcx }
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* r11 }<-- pushed by hypercall page
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* rsp->rax }
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*/
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SYM_CODE_START(xen_iret)
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UNWIND_HINT_EMPTY
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ANNOTATE_NOENDBR
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pushq $0
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jmp hypercall_iret
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SYM_CODE_END(xen_iret)
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/*
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* XEN pv doesn't use trampoline stack, PER_CPU_VAR(cpu_tss_rw + TSS_sp0) is
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* also the kernel stack. Reusing swapgs_restore_regs_and_return_to_usermode()
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* in XEN pv would cause %rsp to move up to the top of the kernel stack and
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* leave the IRET frame below %rsp, which is dangerous to be corrupted if #NMI
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* interrupts. And swapgs_restore_regs_and_return_to_usermode() pushing the IRET
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* frame at the same address is useless.
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*/
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SYM_CODE_START(xenpv_restore_regs_and_return_to_usermode)
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UNWIND_HINT_REGS
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POP_REGS
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/* stackleak_erase() can work safely on the kernel stack. */
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STACKLEAK_ERASE_NOCLOBBER
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addq $8, %rsp /* skip regs->orig_ax */
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jmp xen_iret
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SYM_CODE_END(xenpv_restore_regs_and_return_to_usermode)
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/*
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* Xen handles syscall callbacks much like ordinary exceptions, which
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* means we have:
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* - kernel gs
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* - kernel rsp
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* - an iret-like stack frame on the stack (including rcx and r11):
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* ss
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* rsp
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* rflags
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* cs
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* rip
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* r11
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* rsp->rcx
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*/
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/* Normal 64-bit system call target */
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SYM_CODE_START(xen_entry_SYSCALL_64)
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UNWIND_HINT_ENTRY
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ENDBR
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popq %rcx
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popq %r11
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/*
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* Neither Xen nor the kernel really knows what the old SS and
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* CS were. The kernel expects __USER_DS and __USER_CS, so
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* report those values even though Xen will guess its own values.
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*/
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movq $__USER_DS, 4*8(%rsp)
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movq $__USER_CS, 1*8(%rsp)
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jmp entry_SYSCALL_64_after_hwframe
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SYM_CODE_END(xen_entry_SYSCALL_64)
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#ifdef CONFIG_IA32_EMULATION
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/* 32-bit compat syscall target */
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SYM_CODE_START(xen_entry_SYSCALL_compat)
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UNWIND_HINT_ENTRY
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ENDBR
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popq %rcx
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popq %r11
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/*
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* Neither Xen nor the kernel really knows what the old SS and
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* CS were. The kernel expects __USER_DS and __USER32_CS, so
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* report those values even though Xen will guess its own values.
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*/
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movq $__USER_DS, 4*8(%rsp)
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movq $__USER32_CS, 1*8(%rsp)
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jmp entry_SYSCALL_compat_after_hwframe
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SYM_CODE_END(xen_entry_SYSCALL_compat)
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/* 32-bit compat sysenter target */
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SYM_CODE_START(xen_entry_SYSENTER_compat)
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UNWIND_HINT_ENTRY
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ENDBR
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/*
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* NB: Xen is polite and clears TF from EFLAGS for us. This means
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* that we don't need to guard against single step exceptions here.
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*/
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popq %rcx
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popq %r11
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/*
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* Neither Xen nor the kernel really knows what the old SS and
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* CS were. The kernel expects __USER_DS and __USER32_CS, so
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* report those values even though Xen will guess its own values.
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*/
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movq $__USER_DS, 4*8(%rsp)
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movq $__USER32_CS, 1*8(%rsp)
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jmp entry_SYSENTER_compat_after_hwframe
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SYM_CODE_END(xen_entry_SYSENTER_compat)
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#else /* !CONFIG_IA32_EMULATION */
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SYM_CODE_START(xen_entry_SYSCALL_compat)
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SYM_CODE_START(xen_entry_SYSENTER_compat)
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UNWIND_HINT_ENTRY
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ENDBR
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lea 16(%rsp), %rsp /* strip %rcx, %r11 */
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mov $-ENOSYS, %rax
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pushq $0
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jmp hypercall_iret
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SYM_CODE_END(xen_entry_SYSENTER_compat)
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SYM_CODE_END(xen_entry_SYSCALL_compat)
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#endif /* CONFIG_IA32_EMULATION */
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