427 lines
11 KiB
C
427 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Intel IXP4xx Expansion Bus Controller
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* Copyright (C) 2021 Linaro Ltd.
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*
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* Author: Linus Walleij <linus.walleij@linaro.org>
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*/
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#include <linux/bitfield.h>
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#include <linux/bits.h>
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/log2.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#define IXP4XX_EXP_NUM_CS 8
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#define IXP4XX_EXP_TIMING_CS0 0x00
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#define IXP4XX_EXP_TIMING_CS1 0x04
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#define IXP4XX_EXP_TIMING_CS2 0x08
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#define IXP4XX_EXP_TIMING_CS3 0x0c
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#define IXP4XX_EXP_TIMING_CS4 0x10
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#define IXP4XX_EXP_TIMING_CS5 0x14
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#define IXP4XX_EXP_TIMING_CS6 0x18
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#define IXP4XX_EXP_TIMING_CS7 0x1c
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/* Bits inside each CS timing register */
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#define IXP4XX_EXP_TIMING_STRIDE 0x04
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#define IXP4XX_EXP_CS_EN BIT(31)
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#define IXP456_EXP_PAR_EN BIT(30) /* Only on IXP45x and IXP46x */
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#define IXP4XX_EXP_T1_MASK GENMASK(28, 27)
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#define IXP4XX_EXP_T1_SHIFT 28
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#define IXP4XX_EXP_T2_MASK GENMASK(27, 26)
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#define IXP4XX_EXP_T2_SHIFT 26
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#define IXP4XX_EXP_T3_MASK GENMASK(25, 22)
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#define IXP4XX_EXP_T3_SHIFT 22
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#define IXP4XX_EXP_T4_MASK GENMASK(21, 20)
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#define IXP4XX_EXP_T4_SHIFT 20
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#define IXP4XX_EXP_T5_MASK GENMASK(19, 16)
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#define IXP4XX_EXP_T5_SHIFT 16
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#define IXP4XX_EXP_CYC_TYPE_MASK GENMASK(15, 14)
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#define IXP4XX_EXP_CYC_TYPE_SHIFT 14
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#define IXP4XX_EXP_SIZE_MASK GENMASK(13, 10)
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#define IXP4XX_EXP_SIZE_SHIFT 10
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#define IXP4XX_EXP_CNFG_0 BIT(9) /* Always zero */
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#define IXP43X_EXP_SYNC_INTEL BIT(8) /* Only on IXP43x */
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#define IXP43X_EXP_EXP_CHIP BIT(7) /* Only on IXP43x, dangerous to touch on IXP42x */
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#define IXP4XX_EXP_BYTE_RD16 BIT(6)
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#define IXP4XX_EXP_HRDY_POL BIT(5) /* Only on IXP42x */
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#define IXP4XX_EXP_MUX_EN BIT(4)
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#define IXP4XX_EXP_SPLT_EN BIT(3)
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#define IXP4XX_EXP_WORD BIT(2) /* Always zero */
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#define IXP4XX_EXP_WR_EN BIT(1)
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#define IXP4XX_EXP_BYTE_EN BIT(0)
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#define IXP4XX_EXP_CNFG0 0x20
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#define IXP4XX_EXP_CNFG0_MEM_MAP BIT(31)
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#define IXP4XX_EXP_CNFG1 0x24
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#define IXP4XX_EXP_BOOT_BASE 0x00000000
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#define IXP4XX_EXP_NORMAL_BASE 0x50000000
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#define IXP4XX_EXP_STRIDE 0x01000000
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/* Fuses on the IXP43x */
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#define IXP43X_EXP_UNIT_FUSE_RESET 0x28
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#define IXP43x_EXP_FUSE_SPEED_MASK GENMASK(23, 22)
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/* Number of device tree values in "reg" */
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#define IXP4XX_OF_REG_SIZE 3
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struct ixp4xx_eb {
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struct device *dev;
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struct regmap *rmap;
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u32 bus_base;
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bool is_42x;
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bool is_43x;
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};
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struct ixp4xx_exp_tim_prop {
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const char *prop;
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u32 max;
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u32 mask;
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u16 shift;
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};
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static const struct ixp4xx_exp_tim_prop ixp4xx_exp_tim_props[] = {
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{
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.prop = "intel,ixp4xx-eb-t1",
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.max = 3,
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.mask = IXP4XX_EXP_T1_MASK,
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.shift = IXP4XX_EXP_T1_SHIFT,
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},
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{
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.prop = "intel,ixp4xx-eb-t2",
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.max = 3,
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.mask = IXP4XX_EXP_T2_MASK,
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.shift = IXP4XX_EXP_T2_SHIFT,
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},
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{
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.prop = "intel,ixp4xx-eb-t3",
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.max = 15,
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.mask = IXP4XX_EXP_T3_MASK,
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.shift = IXP4XX_EXP_T3_SHIFT,
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},
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{
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.prop = "intel,ixp4xx-eb-t4",
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.max = 3,
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.mask = IXP4XX_EXP_T4_MASK,
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.shift = IXP4XX_EXP_T4_SHIFT,
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},
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{
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.prop = "intel,ixp4xx-eb-t5",
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.max = 15,
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.mask = IXP4XX_EXP_T5_MASK,
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.shift = IXP4XX_EXP_T5_SHIFT,
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},
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{
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.prop = "intel,ixp4xx-eb-byte-access-on-halfword",
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.max = 1,
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.mask = IXP4XX_EXP_BYTE_RD16,
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},
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{
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.prop = "intel,ixp4xx-eb-hpi-hrdy-pol-high",
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.max = 1,
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.mask = IXP4XX_EXP_HRDY_POL,
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},
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{
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.prop = "intel,ixp4xx-eb-mux-address-and-data",
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.max = 1,
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.mask = IXP4XX_EXP_MUX_EN,
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},
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{
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.prop = "intel,ixp4xx-eb-ahb-split-transfers",
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.max = 1,
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.mask = IXP4XX_EXP_SPLT_EN,
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},
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{
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.prop = "intel,ixp4xx-eb-write-enable",
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.max = 1,
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.mask = IXP4XX_EXP_WR_EN,
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},
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{
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.prop = "intel,ixp4xx-eb-byte-access",
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.max = 1,
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.mask = IXP4XX_EXP_BYTE_EN,
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},
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};
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static void ixp4xx_exp_setup_chipselect(struct ixp4xx_eb *eb,
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struct device_node *np,
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u32 cs_index,
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u32 cs_size)
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{
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u32 cs_cfg;
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u32 val;
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u32 cur_cssize;
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u32 cs_order;
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int ret;
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int i;
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if (eb->is_42x && (cs_index > 7)) {
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dev_err(eb->dev,
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"invalid chipselect %u, we only support 0-7\n",
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cs_index);
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return;
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}
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if (eb->is_43x && (cs_index > 3)) {
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dev_err(eb->dev,
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"invalid chipselect %u, we only support 0-3\n",
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cs_index);
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return;
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}
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/* Several chip selects can be joined into one device */
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if (cs_size > IXP4XX_EXP_STRIDE)
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cur_cssize = IXP4XX_EXP_STRIDE;
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else
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cur_cssize = cs_size;
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/*
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* The following will read/modify/write the configuration for one
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* chipselect, attempting to leave the boot defaults in place unless
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* something is explicitly defined.
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*/
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regmap_read(eb->rmap, IXP4XX_EXP_TIMING_CS0 +
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IXP4XX_EXP_TIMING_STRIDE * cs_index, &cs_cfg);
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dev_info(eb->dev, "CS%d at %#08x, size %#08x, config before: %#08x\n",
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cs_index, eb->bus_base + IXP4XX_EXP_STRIDE * cs_index,
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cur_cssize, cs_cfg);
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/* Size set-up first align to 2^9 .. 2^24 */
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cur_cssize = roundup_pow_of_two(cur_cssize);
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if (cur_cssize < 512)
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cur_cssize = 512;
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cs_order = ilog2(cur_cssize);
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if (cs_order < 9 || cs_order > 24) {
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dev_err(eb->dev, "illegal size order %d\n", cs_order);
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return;
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}
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dev_dbg(eb->dev, "CS%d size order: %d\n", cs_index, cs_order);
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cs_cfg &= ~(IXP4XX_EXP_SIZE_MASK);
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cs_cfg |= ((cs_order - 9) << IXP4XX_EXP_SIZE_SHIFT);
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for (i = 0; i < ARRAY_SIZE(ixp4xx_exp_tim_props); i++) {
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const struct ixp4xx_exp_tim_prop *ip = &ixp4xx_exp_tim_props[i];
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/* All are regular u32 values */
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ret = of_property_read_u32(np, ip->prop, &val);
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if (ret)
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continue;
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/* Handle bools (single bits) first */
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if (ip->max == 1) {
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if (val)
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cs_cfg |= ip->mask;
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else
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cs_cfg &= ~ip->mask;
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dev_info(eb->dev, "CS%d %s %s\n", cs_index,
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val ? "enabled" : "disabled",
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ip->prop);
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continue;
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}
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if (val > ip->max) {
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dev_err(eb->dev,
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"CS%d too high value for %s: %u, capped at %u\n",
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cs_index, ip->prop, val, ip->max);
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val = ip->max;
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}
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/* This assumes max value fills all the assigned bits (and it does) */
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cs_cfg &= ~ip->mask;
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cs_cfg |= (val << ip->shift);
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dev_info(eb->dev, "CS%d set %s to %u\n", cs_index, ip->prop, val);
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}
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ret = of_property_read_u32(np, "intel,ixp4xx-eb-cycle-type", &val);
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if (!ret) {
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if (val > 3) {
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dev_err(eb->dev, "illegal cycle type %d\n", val);
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return;
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}
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dev_info(eb->dev, "CS%d set cycle type %d\n", cs_index, val);
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cs_cfg &= ~IXP4XX_EXP_CYC_TYPE_MASK;
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cs_cfg |= val << IXP4XX_EXP_CYC_TYPE_SHIFT;
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}
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if (eb->is_43x) {
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/* Should always be zero */
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cs_cfg &= ~IXP4XX_EXP_WORD;
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/*
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* This bit for Intel strata flash is currently unused, but let's
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* report it if we find one.
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*/
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if (cs_cfg & IXP43X_EXP_SYNC_INTEL)
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dev_info(eb->dev, "claims to be Intel strata flash\n");
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}
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cs_cfg |= IXP4XX_EXP_CS_EN;
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regmap_write(eb->rmap,
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IXP4XX_EXP_TIMING_CS0 + IXP4XX_EXP_TIMING_STRIDE * cs_index,
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cs_cfg);
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dev_info(eb->dev, "CS%d wrote %#08x into CS config\n", cs_index, cs_cfg);
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/*
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* If several chip selects are joined together into one big
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* device area, we call ourselves recursively for each successive
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* chip select. For a 32MB flash chip this results in two calls
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* for example.
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*/
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if (cs_size > IXP4XX_EXP_STRIDE)
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ixp4xx_exp_setup_chipselect(eb, np,
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cs_index + 1,
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cs_size - IXP4XX_EXP_STRIDE);
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}
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static void ixp4xx_exp_setup_child(struct ixp4xx_eb *eb,
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struct device_node *np)
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{
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u32 cs_sizes[IXP4XX_EXP_NUM_CS];
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int num_regs;
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u32 csindex;
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u32 cssize;
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int ret;
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int i;
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num_regs = of_property_count_elems_of_size(np, "reg", IXP4XX_OF_REG_SIZE);
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if (num_regs <= 0)
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return;
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dev_dbg(eb->dev, "child %s has %d register sets\n",
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of_node_full_name(np), num_regs);
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for (csindex = 0; csindex < IXP4XX_EXP_NUM_CS; csindex++)
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cs_sizes[csindex] = 0;
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for (i = 0; i < num_regs; i++) {
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u32 rbase, rsize;
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ret = of_property_read_u32_index(np, "reg",
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i * IXP4XX_OF_REG_SIZE, &csindex);
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if (ret)
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break;
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ret = of_property_read_u32_index(np, "reg",
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i * IXP4XX_OF_REG_SIZE + 1, &rbase);
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if (ret)
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break;
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ret = of_property_read_u32_index(np, "reg",
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i * IXP4XX_OF_REG_SIZE + 2, &rsize);
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if (ret)
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break;
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if (csindex >= IXP4XX_EXP_NUM_CS) {
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dev_err(eb->dev, "illegal CS %d\n", csindex);
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continue;
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}
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/*
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* The memory window always starts from CS base so we need to add
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* the start and size to get to the size from the start of the CS
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* base. For example if CS0 is at 0x50000000 and the reg is
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* <0 0xe40000 0x40000> the size is e80000.
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*
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* Roof this if we have several regs setting the same CS.
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*/
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cssize = rbase + rsize;
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dev_dbg(eb->dev, "CS%d size %#08x\n", csindex, cssize);
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if (cs_sizes[csindex] < cssize)
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cs_sizes[csindex] = cssize;
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}
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for (csindex = 0; csindex < IXP4XX_EXP_NUM_CS; csindex++) {
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cssize = cs_sizes[csindex];
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if (!cssize)
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continue;
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/* Just this one, so set it up and return */
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ixp4xx_exp_setup_chipselect(eb, np, csindex, cssize);
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}
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}
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static int ixp4xx_exp_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct device_node *np = dev->of_node;
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struct ixp4xx_eb *eb;
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struct device_node *child;
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bool have_children = false;
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u32 val;
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int ret;
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eb = devm_kzalloc(dev, sizeof(*eb), GFP_KERNEL);
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if (!eb)
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return -ENOMEM;
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eb->dev = dev;
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eb->is_42x = of_device_is_compatible(np, "intel,ixp42x-expansion-bus-controller");
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eb->is_43x = of_device_is_compatible(np, "intel,ixp43x-expansion-bus-controller");
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eb->rmap = syscon_node_to_regmap(np);
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if (IS_ERR(eb->rmap))
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return dev_err_probe(dev, PTR_ERR(eb->rmap), "no regmap\n");
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/* We check that the regmap work only on first read */
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ret = regmap_read(eb->rmap, IXP4XX_EXP_CNFG0, &val);
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if (ret)
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return dev_err_probe(dev, ret, "cannot read regmap\n");
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if (val & IXP4XX_EXP_CNFG0_MEM_MAP)
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eb->bus_base = IXP4XX_EXP_BOOT_BASE;
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else
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eb->bus_base = IXP4XX_EXP_NORMAL_BASE;
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dev_info(dev, "expansion bus at %08x\n", eb->bus_base);
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if (eb->is_43x) {
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/* Check some fuses */
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regmap_read(eb->rmap, IXP43X_EXP_UNIT_FUSE_RESET, &val);
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switch (FIELD_GET(IXP43x_EXP_FUSE_SPEED_MASK, val)) {
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case 0:
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dev_info(dev, "IXP43x at 533 MHz\n");
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break;
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case 1:
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dev_info(dev, "IXP43x at 400 MHz\n");
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break;
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case 2:
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dev_info(dev, "IXP43x at 667 MHz\n");
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break;
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default:
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dev_info(dev, "IXP43x unknown speed\n");
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break;
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}
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}
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/* Walk over the child nodes and see what chipselects we use */
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for_each_available_child_of_node(np, child) {
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ixp4xx_exp_setup_child(eb, child);
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/* We have at least one child */
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have_children = true;
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}
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if (have_children)
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return of_platform_default_populate(np, NULL, dev);
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return 0;
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}
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static const struct of_device_id ixp4xx_exp_of_match[] = {
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{ .compatible = "intel,ixp42x-expansion-bus-controller", },
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{ .compatible = "intel,ixp43x-expansion-bus-controller", },
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{ .compatible = "intel,ixp45x-expansion-bus-controller", },
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{ .compatible = "intel,ixp46x-expansion-bus-controller", },
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{ }
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};
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static struct platform_driver ixp4xx_exp_driver = {
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.probe = ixp4xx_exp_probe,
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.driver = {
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.name = "intel-extbus",
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.of_match_table = ixp4xx_exp_of_match,
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},
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};
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module_platform_driver(ixp4xx_exp_driver);
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MODULE_AUTHOR("Linus Walleij <linus.walleij@linaro.org>");
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MODULE_DESCRIPTION("Intel IXP4xx external bus driver");
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MODULE_LICENSE("GPL");
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