565 lines
13 KiB
C
565 lines
13 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* X1000 SoC CGU driver
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* Copyright (c) 2019 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
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*/
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#include <linux/clk-provider.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/rational.h>
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#include <dt-bindings/clock/ingenic,x1000-cgu.h>
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#include "cgu.h"
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#include "pm.h"
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/* CGU register offsets */
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#define CGU_REG_CPCCR 0x00
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#define CGU_REG_APLL 0x10
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#define CGU_REG_MPLL 0x14
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#define CGU_REG_CLKGR 0x20
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#define CGU_REG_OPCR 0x24
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#define CGU_REG_DDRCDR 0x2c
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#define CGU_REG_USBPCR 0x3c
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#define CGU_REG_USBPCR1 0x48
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#define CGU_REG_USBCDR 0x50
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#define CGU_REG_MACCDR 0x54
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#define CGU_REG_I2SCDR 0x60
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#define CGU_REG_LPCDR 0x64
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#define CGU_REG_MSC0CDR 0x68
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#define CGU_REG_I2SCDR1 0x70
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#define CGU_REG_SSICDR 0x74
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#define CGU_REG_CIMCDR 0x7c
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#define CGU_REG_PCMCDR 0x84
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#define CGU_REG_MSC1CDR 0xa4
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#define CGU_REG_CMP_INTR 0xb0
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#define CGU_REG_CMP_INTRE 0xb4
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#define CGU_REG_DRCG 0xd0
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#define CGU_REG_CPCSR 0xd4
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#define CGU_REG_PCMCDR1 0xe0
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#define CGU_REG_MACPHYC 0xe8
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/* bits within the OPCR register */
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#define OPCR_SPENDN0 BIT(7)
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#define OPCR_SPENDN1 BIT(6)
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/* bits within the USBPCR register */
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#define USBPCR_SIDDQ BIT(21)
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#define USBPCR_OTG_DISABLE BIT(20)
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/* bits within the USBPCR1 register */
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#define USBPCR1_REFCLKSEL_SHIFT 26
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#define USBPCR1_REFCLKSEL_MASK (0x3 << USBPCR1_REFCLKSEL_SHIFT)
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#define USBPCR1_REFCLKSEL_CORE (0x2 << USBPCR1_REFCLKSEL_SHIFT)
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#define USBPCR1_REFCLKDIV_SHIFT 24
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#define USBPCR1_REFCLKDIV_MASK (0x3 << USBPCR1_REFCLKDIV_SHIFT)
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#define USBPCR1_REFCLKDIV_48 (0x2 << USBPCR1_REFCLKDIV_SHIFT)
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#define USBPCR1_REFCLKDIV_24 (0x1 << USBPCR1_REFCLKDIV_SHIFT)
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#define USBPCR1_REFCLKDIV_12 (0x0 << USBPCR1_REFCLKDIV_SHIFT)
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static struct ingenic_cgu *cgu;
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static unsigned long x1000_otg_phy_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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u32 usbpcr1;
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unsigned refclk_div;
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usbpcr1 = readl(cgu->base + CGU_REG_USBPCR1);
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refclk_div = usbpcr1 & USBPCR1_REFCLKDIV_MASK;
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switch (refclk_div) {
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case USBPCR1_REFCLKDIV_12:
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return 12000000;
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case USBPCR1_REFCLKDIV_24:
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return 24000000;
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case USBPCR1_REFCLKDIV_48:
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return 48000000;
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}
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return parent_rate;
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}
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static long x1000_otg_phy_round_rate(struct clk_hw *hw, unsigned long req_rate,
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unsigned long *parent_rate)
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{
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if (req_rate < 18000000)
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return 12000000;
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if (req_rate < 36000000)
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return 24000000;
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return 48000000;
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}
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static int x1000_otg_phy_set_rate(struct clk_hw *hw, unsigned long req_rate,
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unsigned long parent_rate)
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{
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unsigned long flags;
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u32 usbpcr1, div_bits;
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switch (req_rate) {
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case 12000000:
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div_bits = USBPCR1_REFCLKDIV_12;
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break;
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case 24000000:
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div_bits = USBPCR1_REFCLKDIV_24;
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break;
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case 48000000:
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div_bits = USBPCR1_REFCLKDIV_48;
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break;
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default:
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return -EINVAL;
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}
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spin_lock_irqsave(&cgu->lock, flags);
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usbpcr1 = readl(cgu->base + CGU_REG_USBPCR1);
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usbpcr1 &= ~USBPCR1_REFCLKDIV_MASK;
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usbpcr1 |= div_bits;
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writel(usbpcr1, cgu->base + CGU_REG_USBPCR1);
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spin_unlock_irqrestore(&cgu->lock, flags);
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return 0;
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}
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static int x1000_usb_phy_enable(struct clk_hw *hw)
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{
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void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR;
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void __iomem *reg_usbpcr = cgu->base + CGU_REG_USBPCR;
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writel(readl(reg_opcr) | OPCR_SPENDN0, reg_opcr);
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writel(readl(reg_usbpcr) & ~USBPCR_OTG_DISABLE & ~USBPCR_SIDDQ, reg_usbpcr);
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return 0;
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}
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static void x1000_usb_phy_disable(struct clk_hw *hw)
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{
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void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR;
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void __iomem *reg_usbpcr = cgu->base + CGU_REG_USBPCR;
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writel(readl(reg_opcr) & ~OPCR_SPENDN0, reg_opcr);
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writel(readl(reg_usbpcr) | USBPCR_OTG_DISABLE | USBPCR_SIDDQ, reg_usbpcr);
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}
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static int x1000_usb_phy_is_enabled(struct clk_hw *hw)
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{
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void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR;
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void __iomem *reg_usbpcr = cgu->base + CGU_REG_USBPCR;
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return (readl(reg_opcr) & OPCR_SPENDN0) &&
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!(readl(reg_usbpcr) & USBPCR_SIDDQ) &&
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!(readl(reg_usbpcr) & USBPCR_OTG_DISABLE);
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}
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static const struct clk_ops x1000_otg_phy_ops = {
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.recalc_rate = x1000_otg_phy_recalc_rate,
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.round_rate = x1000_otg_phy_round_rate,
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.set_rate = x1000_otg_phy_set_rate,
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.enable = x1000_usb_phy_enable,
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.disable = x1000_usb_phy_disable,
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.is_enabled = x1000_usb_phy_is_enabled,
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};
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static void
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x1000_i2spll_calc_m_n_od(const struct ingenic_cgu_pll_info *pll_info,
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unsigned long rate, unsigned long parent_rate,
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unsigned int *pm, unsigned int *pn, unsigned int *pod)
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{
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const unsigned long m_max = GENMASK(pll_info->m_bits - 1, 0);
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const unsigned long n_max = GENMASK(pll_info->n_bits - 1, 0);
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unsigned long m, n;
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rational_best_approximation(rate, parent_rate, m_max, n_max, &m, &n);
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/* n should not be less than 2*m */
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if (n < 2 * m)
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n = 2 * m;
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*pm = m;
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*pn = n;
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*pod = 1;
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}
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static void
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x1000_i2spll_set_rate_hook(const struct ingenic_cgu_pll_info *pll_info,
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unsigned long rate, unsigned long parent_rate)
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{
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/*
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* Writing 0 causes I2SCDR1.I2SDIV_D to be automatically recalculated
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* based on the current value of I2SCDR.I2SDIV_N, which is needed for
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* the divider to function correctly.
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*/
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writel(0, cgu->base + CGU_REG_I2SCDR1);
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}
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static const s8 pll_od_encoding[8] = {
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0x0, 0x1, -1, 0x2, -1, -1, -1, 0x3,
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};
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static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = {
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/* External clocks */
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[X1000_CLK_EXCLK] = { "ext", CGU_CLK_EXT },
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[X1000_CLK_RTCLK] = { "rtc", CGU_CLK_EXT },
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/* PLLs */
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[X1000_CLK_APLL] = {
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"apll", CGU_CLK_PLL,
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.parents = { X1000_CLK_EXCLK },
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.pll = {
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.reg = CGU_REG_APLL,
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.rate_multiplier = 1,
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.m_shift = 24,
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.m_bits = 7,
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.m_offset = 1,
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.n_shift = 18,
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.n_bits = 5,
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.n_offset = 1,
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.od_shift = 16,
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.od_bits = 2,
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.od_max = 8,
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.od_encoding = pll_od_encoding,
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.bypass_reg = CGU_REG_APLL,
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.bypass_bit = 9,
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.enable_bit = 8,
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.stable_bit = 10,
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},
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},
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[X1000_CLK_MPLL] = {
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"mpll", CGU_CLK_PLL,
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.parents = { X1000_CLK_EXCLK },
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.pll = {
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.reg = CGU_REG_MPLL,
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.rate_multiplier = 1,
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.m_shift = 24,
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.m_bits = 7,
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.m_offset = 1,
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.n_shift = 18,
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.n_bits = 5,
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.n_offset = 1,
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.od_shift = 16,
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.od_bits = 2,
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.od_max = 8,
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.od_encoding = pll_od_encoding,
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.bypass_reg = CGU_REG_MPLL,
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.bypass_bit = 6,
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.enable_bit = 7,
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.stable_bit = 0,
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},
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},
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/* Custom (SoC-specific) OTG PHY */
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[X1000_CLK_OTGPHY] = {
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"otg_phy", CGU_CLK_CUSTOM,
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.parents = { -1, -1, X1000_CLK_EXCLK, -1 },
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.custom = { &x1000_otg_phy_ops },
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},
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/* Muxes & dividers */
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[X1000_CLK_SCLKA] = {
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"sclk_a", CGU_CLK_MUX,
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.parents = { -1, X1000_CLK_EXCLK, X1000_CLK_APLL, -1 },
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.mux = { CGU_REG_CPCCR, 30, 2 },
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},
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[X1000_CLK_CPUMUX] = {
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"cpu_mux", CGU_CLK_MUX,
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.parents = { -1, X1000_CLK_SCLKA, X1000_CLK_MPLL, -1 },
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.mux = { CGU_REG_CPCCR, 28, 2 },
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},
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[X1000_CLK_CPU] = {
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"cpu", CGU_CLK_DIV | CGU_CLK_GATE,
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/*
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* Disabling the CPU clock or any parent clocks will hang the
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* system; mark it critical.
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*/
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.flags = CLK_IS_CRITICAL,
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.parents = { X1000_CLK_CPUMUX },
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.div = { CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1 },
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.gate = { CGU_REG_CLKGR, 30 },
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},
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[X1000_CLK_L2CACHE] = {
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"l2cache", CGU_CLK_DIV,
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/*
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* The L2 cache clock is critical if caches are enabled and
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* disabling it or any parent clocks will hang the system.
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*/
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.flags = CLK_IS_CRITICAL,
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.parents = { X1000_CLK_CPUMUX },
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.div = { CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1 },
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},
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[X1000_CLK_AHB0] = {
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"ahb0", CGU_CLK_MUX | CGU_CLK_DIV,
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.parents = { -1, X1000_CLK_SCLKA, X1000_CLK_MPLL, -1 },
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.mux = { CGU_REG_CPCCR, 26, 2 },
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.div = { CGU_REG_CPCCR, 8, 1, 4, 21, -1, -1 },
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},
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[X1000_CLK_AHB2PMUX] = {
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"ahb2_apb_mux", CGU_CLK_MUX,
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.parents = { -1, X1000_CLK_SCLKA, X1000_CLK_MPLL, -1 },
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.mux = { CGU_REG_CPCCR, 24, 2 },
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},
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[X1000_CLK_AHB2] = {
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"ahb2", CGU_CLK_DIV,
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.parents = { X1000_CLK_AHB2PMUX },
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.div = { CGU_REG_CPCCR, 12, 1, 4, 20, -1, -1 },
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},
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[X1000_CLK_PCLK] = {
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"pclk", CGU_CLK_DIV | CGU_CLK_GATE,
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.parents = { X1000_CLK_AHB2PMUX },
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.div = { CGU_REG_CPCCR, 16, 1, 4, 20, -1, -1 },
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.gate = { CGU_REG_CLKGR, 28 },
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},
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[X1000_CLK_DDR] = {
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"ddr", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
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/*
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* Disabling DDR clock or its parents will render DRAM
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* inaccessible; mark it critical.
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*/
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.flags = CLK_IS_CRITICAL,
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.parents = { -1, X1000_CLK_SCLKA, X1000_CLK_MPLL, -1 },
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.mux = { CGU_REG_DDRCDR, 30, 2 },
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.div = { CGU_REG_DDRCDR, 0, 1, 4, 29, 28, 27 },
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.gate = { CGU_REG_CLKGR, 31 },
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},
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[X1000_CLK_MAC] = {
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"mac", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
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.parents = { X1000_CLK_SCLKA, X1000_CLK_MPLL },
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.mux = { CGU_REG_MACCDR, 31, 1 },
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.div = { CGU_REG_MACCDR, 0, 1, 8, 29, 28, 27 },
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.gate = { CGU_REG_CLKGR, 25 },
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},
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[X1000_CLK_I2SPLLMUX] = {
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"i2s_pll_mux", CGU_CLK_MUX,
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.parents = { X1000_CLK_SCLKA, X1000_CLK_MPLL },
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.mux = { CGU_REG_I2SCDR, 31, 1 },
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},
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[X1000_CLK_I2SPLL] = {
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"i2s_pll", CGU_CLK_PLL,
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.parents = { X1000_CLK_I2SPLLMUX },
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.pll = {
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.reg = CGU_REG_I2SCDR,
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.rate_multiplier = 1,
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.m_shift = 13,
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.m_bits = 9,
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.n_shift = 0,
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.n_bits = 13,
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.calc_m_n_od = x1000_i2spll_calc_m_n_od,
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.set_rate_hook = x1000_i2spll_set_rate_hook,
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},
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},
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[X1000_CLK_I2S] = {
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"i2s", CGU_CLK_MUX,
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.parents = { X1000_CLK_EXCLK, -1, -1, X1000_CLK_I2SPLL },
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/*
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* NOTE: the mux is at bit 30; bit 29 enables the M/N divider.
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* Therefore, the divider is disabled when EXCLK is selected.
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*/
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.mux = { CGU_REG_I2SCDR, 29, 2 },
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},
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[X1000_CLK_LCD] = {
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"lcd", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
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.parents = { X1000_CLK_SCLKA, X1000_CLK_MPLL },
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.mux = { CGU_REG_LPCDR, 31, 1 },
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.div = { CGU_REG_LPCDR, 0, 1, 8, 28, 27, 26 },
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.gate = { CGU_REG_CLKGR, 23 },
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},
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[X1000_CLK_MSCMUX] = {
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"msc_mux", CGU_CLK_MUX,
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.parents = { X1000_CLK_SCLKA, X1000_CLK_MPLL },
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.mux = { CGU_REG_MSC0CDR, 31, 1 },
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},
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[X1000_CLK_MSC0] = {
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"msc0", CGU_CLK_DIV | CGU_CLK_GATE,
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.parents = { X1000_CLK_MSCMUX },
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.div = { CGU_REG_MSC0CDR, 0, 2, 8, 29, 28, 27 },
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.gate = { CGU_REG_CLKGR, 4 },
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},
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[X1000_CLK_MSC1] = {
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"msc1", CGU_CLK_DIV | CGU_CLK_GATE,
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.parents = { X1000_CLK_MSCMUX, -1, -1, -1 },
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.div = { CGU_REG_MSC1CDR, 0, 2, 8, 29, 28, 27 },
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.gate = { CGU_REG_CLKGR, 5 },
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},
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[X1000_CLK_OTG] = {
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"otg", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
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.parents = { X1000_CLK_EXCLK, -1, X1000_CLK_APLL, X1000_CLK_MPLL },
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.mux = { CGU_REG_USBCDR, 30, 2 },
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.div = { CGU_REG_USBCDR, 0, 1, 8, 29, 28, 27 },
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.gate = { CGU_REG_CLKGR, 3 },
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},
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[X1000_CLK_SSIPLL] = {
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"ssi_pll", CGU_CLK_MUX | CGU_CLK_DIV,
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.parents = { X1000_CLK_SCLKA, X1000_CLK_MPLL },
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.mux = { CGU_REG_SSICDR, 31, 1 },
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.div = { CGU_REG_SSICDR, 0, 1, 8, 29, 28, 27 },
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},
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[X1000_CLK_SSIPLL_DIV2] = {
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"ssi_pll_div2", CGU_CLK_FIXDIV,
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.parents = { X1000_CLK_SSIPLL },
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.fixdiv = { 2 },
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},
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[X1000_CLK_SSIMUX] = {
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"ssi_mux", CGU_CLK_MUX,
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.parents = { X1000_CLK_EXCLK, X1000_CLK_SSIPLL_DIV2 },
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.mux = { CGU_REG_SSICDR, 30, 1 },
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},
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[X1000_CLK_EXCLK_DIV512] = {
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"exclk_div512", CGU_CLK_FIXDIV,
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.parents = { X1000_CLK_EXCLK },
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.fixdiv = { 512 },
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},
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[X1000_CLK_RTC] = {
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"rtc_ercs", CGU_CLK_MUX | CGU_CLK_GATE,
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.parents = { X1000_CLK_EXCLK_DIV512, X1000_CLK_RTCLK },
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.mux = { CGU_REG_OPCR, 2, 1},
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.gate = { CGU_REG_CLKGR, 27 },
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},
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|
/* Gate-only clocks */
|
|
|
|
[X1000_CLK_EMC] = {
|
|
"emc", CGU_CLK_GATE,
|
|
.parents = { X1000_CLK_AHB2 },
|
|
.gate = { CGU_REG_CLKGR, 0 },
|
|
},
|
|
|
|
[X1000_CLK_EFUSE] = {
|
|
"efuse", CGU_CLK_GATE,
|
|
.parents = { X1000_CLK_AHB2 },
|
|
.gate = { CGU_REG_CLKGR, 1 },
|
|
},
|
|
|
|
[X1000_CLK_SFC] = {
|
|
"sfc", CGU_CLK_GATE,
|
|
.parents = { X1000_CLK_SSIPLL },
|
|
.gate = { CGU_REG_CLKGR, 2 },
|
|
},
|
|
|
|
[X1000_CLK_I2C0] = {
|
|
"i2c0", CGU_CLK_GATE,
|
|
.parents = { X1000_CLK_PCLK },
|
|
.gate = { CGU_REG_CLKGR, 7 },
|
|
},
|
|
|
|
[X1000_CLK_I2C1] = {
|
|
"i2c1", CGU_CLK_GATE,
|
|
.parents = { X1000_CLK_PCLK },
|
|
.gate = { CGU_REG_CLKGR, 8 },
|
|
},
|
|
|
|
[X1000_CLK_I2C2] = {
|
|
"i2c2", CGU_CLK_GATE,
|
|
.parents = { X1000_CLK_PCLK },
|
|
.gate = { CGU_REG_CLKGR, 9 },
|
|
},
|
|
|
|
[X1000_CLK_AIC] = {
|
|
"aic", CGU_CLK_GATE,
|
|
.parents = { X1000_CLK_EXCLK },
|
|
.gate = { CGU_REG_CLKGR, 11 },
|
|
},
|
|
|
|
[X1000_CLK_UART0] = {
|
|
"uart0", CGU_CLK_GATE,
|
|
.parents = { X1000_CLK_EXCLK },
|
|
.gate = { CGU_REG_CLKGR, 14 },
|
|
},
|
|
|
|
[X1000_CLK_UART1] = {
|
|
"uart1", CGU_CLK_GATE,
|
|
.parents = { X1000_CLK_EXCLK},
|
|
.gate = { CGU_REG_CLKGR, 15 },
|
|
},
|
|
|
|
[X1000_CLK_UART2] = {
|
|
"uart2", CGU_CLK_GATE,
|
|
.parents = { X1000_CLK_EXCLK },
|
|
.gate = { CGU_REG_CLKGR, 16 },
|
|
},
|
|
|
|
[X1000_CLK_TCU] = {
|
|
"tcu", CGU_CLK_GATE,
|
|
.parents = { X1000_CLK_EXCLK },
|
|
.gate = { CGU_REG_CLKGR, 18 },
|
|
},
|
|
|
|
[X1000_CLK_SSI] = {
|
|
"ssi", CGU_CLK_GATE,
|
|
.parents = { X1000_CLK_SSIMUX },
|
|
.gate = { CGU_REG_CLKGR, 19 },
|
|
},
|
|
|
|
[X1000_CLK_OST] = {
|
|
"ost", CGU_CLK_GATE,
|
|
.parents = { X1000_CLK_EXCLK },
|
|
.gate = { CGU_REG_CLKGR, 20 },
|
|
},
|
|
|
|
[X1000_CLK_PDMA] = {
|
|
"pdma", CGU_CLK_GATE,
|
|
.parents = { X1000_CLK_EXCLK },
|
|
.gate = { CGU_REG_CLKGR, 21 },
|
|
},
|
|
};
|
|
|
|
static void __init x1000_cgu_init(struct device_node *np)
|
|
{
|
|
int retval;
|
|
|
|
cgu = ingenic_cgu_new(x1000_cgu_clocks,
|
|
ARRAY_SIZE(x1000_cgu_clocks), np);
|
|
if (!cgu) {
|
|
pr_err("%s: failed to initialise CGU\n", __func__);
|
|
return;
|
|
}
|
|
|
|
retval = ingenic_cgu_register_clocks(cgu);
|
|
if (retval) {
|
|
pr_err("%s: failed to register CGU Clocks\n", __func__);
|
|
return;
|
|
}
|
|
|
|
ingenic_cgu_register_syscore_ops(cgu);
|
|
}
|
|
/*
|
|
* CGU has some children devices, this is useful for probing children devices
|
|
* in the case where the device node is compatible with "simple-mfd".
|
|
*/
|
|
CLK_OF_DECLARE_DRIVER(x1000_cgu, "ingenic,x1000-cgu", x1000_cgu_init);
|