154 lines
4.5 KiB
C
154 lines
4.5 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2022 Collabora Ltd.
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* Author: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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*/
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#include <dt-bindings/clock/mediatek,mt6795-clk.h>
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#include <dt-bindings/reset/mediatek,mt6795-resets.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include "clk-cpumux.h"
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#include "clk-gate.h"
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#include "clk-mtk.h"
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#include "reset.h"
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#define GATE_ICG(_id, _name, _parent, _shift) \
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GATE_MTK(_id, _name, _parent, &infra_cg_regs, \
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_shift, &mtk_clk_gate_ops_no_setclr)
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static const struct mtk_gate_regs infra_cg_regs = {
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.set_ofs = 0x0040,
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.clr_ofs = 0x0044,
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.sta_ofs = 0x0048,
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};
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static const char * const ca53_c0_parents[] = {
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"clk26m",
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"armca53pll",
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"mainpll",
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"univpll"
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};
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static const char * const ca53_c1_parents[] = {
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"clk26m",
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"armca53pll",
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"mainpll",
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"univpll"
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};
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static const struct mtk_composite cpu_muxes[] = {
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MUX(CLK_INFRA_CA53_C0_SEL, "infra_ca53_c0_sel", ca53_c0_parents, 0x00, 0, 2),
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MUX(CLK_INFRA_CA53_C1_SEL, "infra_ca53_c1_sel", ca53_c1_parents, 0x00, 2, 2),
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};
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static const struct mtk_gate infra_gates[] = {
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GATE_ICG(CLK_INFRA_DBGCLK, "infra_dbgclk", "axi_sel", 0),
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GATE_ICG(CLK_INFRA_SMI, "infra_smi", "mm_sel", 1),
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GATE_ICG(CLK_INFRA_AUDIO, "infra_audio", "aud_intbus_sel", 5),
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GATE_ICG(CLK_INFRA_GCE, "infra_gce", "axi_sel", 6),
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GATE_ICG(CLK_INFRA_L2C_SRAM, "infra_l2c_sram", "axi_sel", 7),
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GATE_ICG(CLK_INFRA_M4U, "infra_m4u", "mem_sel", 8),
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GATE_ICG(CLK_INFRA_MD1MCU, "infra_md1mcu", "clk26m", 9),
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GATE_ICG(CLK_INFRA_MD1BUS, "infra_md1bus", "axi_sel", 10),
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GATE_ICG(CLK_INFRA_MD1DBB, "infra_dbb", "axi_sel", 11),
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GATE_ICG(CLK_INFRA_DEVICE_APC, "infra_devapc", "clk26m", 12),
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GATE_ICG(CLK_INFRA_TRNG, "infra_trng", "axi_sel", 13),
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GATE_ICG(CLK_INFRA_MD1LTE, "infra_md1lte", "axi_sel", 14),
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GATE_ICG(CLK_INFRA_CPUM, "infra_cpum", "cpum_ck", 15),
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GATE_ICG(CLK_INFRA_KP, "infra_kp", "axi_sel", 16),
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};
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static u16 infra_ao_rst_ofs[] = { 0x30, 0x34 };
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static u16 infra_ao_idx_map[] = {
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[MT6795_INFRA_RST0_SCPSYS_RST] = 0 * RST_NR_PER_BANK + 5,
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[MT6795_INFRA_RST0_PMIC_WRAP_RST] = 0 * RST_NR_PER_BANK + 7,
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[MT6795_INFRA_RST1_MIPI_DSI_RST] = 1 * RST_NR_PER_BANK + 4,
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[MT6795_INFRA_RST1_MIPI_CSI_RST] = 1 * RST_NR_PER_BANK + 7,
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[MT6795_INFRA_RST1_MM_IOMMU_RST] = 1 * RST_NR_PER_BANK + 15,
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};
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static const struct mtk_clk_rst_desc clk_rst_desc = {
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.version = MTK_RST_SET_CLR,
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.rst_bank_ofs = infra_ao_rst_ofs,
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.rst_bank_nr = ARRAY_SIZE(infra_ao_rst_ofs),
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.rst_idx_map = infra_ao_idx_map,
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.rst_idx_map_nr = ARRAY_SIZE(infra_ao_idx_map),
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};
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static const struct of_device_id of_match_clk_mt6795_infracfg[] = {
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{ .compatible = "mediatek,mt6795-infracfg" },
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{ /* sentinel */ }
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};
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static int clk_mt6795_infracfg_probe(struct platform_device *pdev)
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{
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struct clk_hw_onecell_data *clk_data;
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struct device_node *node = pdev->dev.of_node;
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void __iomem *base;
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int ret;
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base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(base))
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return PTR_ERR(base);
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clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
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if (!clk_data)
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return -ENOMEM;
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ret = mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
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if (ret)
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goto free_clk_data;
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ret = mtk_clk_register_gates(&pdev->dev, node, infra_gates,
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ARRAY_SIZE(infra_gates), clk_data);
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if (ret)
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goto free_clk_data;
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ret = mtk_clk_register_cpumuxes(&pdev->dev, node, cpu_muxes,
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ARRAY_SIZE(cpu_muxes), clk_data);
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if (ret)
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goto unregister_gates;
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ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
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if (ret)
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goto unregister_cpumuxes;
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return 0;
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unregister_cpumuxes:
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mtk_clk_unregister_cpumuxes(cpu_muxes, ARRAY_SIZE(cpu_muxes), clk_data);
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unregister_gates:
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mtk_clk_unregister_gates(infra_gates, ARRAY_SIZE(infra_gates), clk_data);
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free_clk_data:
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mtk_free_clk_data(clk_data);
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return ret;
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}
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static int clk_mt6795_infracfg_remove(struct platform_device *pdev)
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{
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struct device_node *node = pdev->dev.of_node;
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struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
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of_clk_del_provider(node);
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mtk_clk_unregister_cpumuxes(cpu_muxes, ARRAY_SIZE(cpu_muxes), clk_data);
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mtk_clk_unregister_gates(infra_gates, ARRAY_SIZE(infra_gates), clk_data);
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mtk_free_clk_data(clk_data);
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return 0;
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}
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static struct platform_driver clk_mt6795_infracfg_drv = {
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.driver = {
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.name = "clk-mt6795-infracfg",
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.of_match_table = of_match_clk_mt6795_infracfg,
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},
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.probe = clk_mt6795_infracfg_probe,
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.remove = clk_mt6795_infracfg_remove,
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};
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module_platform_driver(clk_mt6795_infracfg_drv);
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MODULE_DESCRIPTION("MediaTek MT6795 infracfg clocks driver");
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MODULE_LICENSE("GPL");
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