467 lines
12 KiB
C
467 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* R-Car Gen4 Clock Pulse Generator
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*
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* Copyright (C) 2021 Renesas Electronics Corp.
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*
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* Based on rcar-gen3-cpg.c
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*
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* Copyright (C) 2015-2018 Glider bvba
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* Copyright (C) 2019 Renesas Electronics Corp.
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*/
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/device.h>
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/slab.h>
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#include "renesas-cpg-mssr.h"
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#include "rcar-gen4-cpg.h"
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#include "rcar-cpg-lib.h"
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static const struct rcar_gen4_cpg_pll_config *cpg_pll_config __initdata;
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static unsigned int cpg_clk_extalr __initdata;
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static u32 cpg_mode __initdata;
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#define CPG_PLLECR 0x0820 /* PLL Enable Control Register */
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#define CPG_PLLECR_PLLST(n) BIT(8 + ((n) < 3 ? (n) - 1 : \
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(n) > 3 ? (n) + 1 : n)) /* PLLn Circuit Status */
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#define CPG_PLL1CR0 0x830 /* PLLn Control Registers */
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#define CPG_PLL1CR1 0x8b0
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#define CPG_PLL2CR0 0x834
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#define CPG_PLL2CR1 0x8b8
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#define CPG_PLL3CR0 0x83c
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#define CPG_PLL3CR1 0x8c0
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#define CPG_PLL4CR0 0x844
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#define CPG_PLL4CR1 0x8c8
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#define CPG_PLL6CR0 0x84c
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#define CPG_PLL6CR1 0x8d8
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#define CPG_PLLxCR0_KICK BIT(31)
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#define CPG_PLLxCR0_NI GENMASK(27, 20) /* Integer mult. factor */
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#define CPG_PLLxCR0_SSMODE GENMASK(18, 16) /* PLL mode */
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#define CPG_PLLxCR0_SSMODE_FM BIT(18) /* Fractional Multiplication */
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#define CPG_PLLxCR0_SSMODE_DITH BIT(17) /* Frequency Dithering */
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#define CPG_PLLxCR0_SSMODE_CENT BIT(16) /* Center (vs. Down) Spread Dithering */
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#define CPG_PLLxCR0_SSFREQ GENMASK(14, 8) /* SSCG Modulation Frequency */
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#define CPG_PLLxCR0_SSDEPT GENMASK(6, 0) /* SSCG Modulation Depth */
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#define SSMODE_FM BIT(2) /* Fractional Multiplication */
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#define SSMODE_DITHER BIT(1) /* Frequency Dithering */
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#define SSMODE_CENTER BIT(0) /* Center (vs. Down) Spread Dithering */
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/* PLL Clocks */
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struct cpg_pll_clk {
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struct clk_hw hw;
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void __iomem *pllcr0_reg;
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void __iomem *pllecr_reg;
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u32 pllecr_pllst_mask;
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};
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#define to_pll_clk(_hw) container_of(_hw, struct cpg_pll_clk, hw)
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static unsigned long cpg_pll_clk_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct cpg_pll_clk *pll_clk = to_pll_clk(hw);
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unsigned int mult;
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mult = FIELD_GET(CPG_PLLxCR0_NI, readl(pll_clk->pllcr0_reg)) + 1;
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return parent_rate * mult * 2;
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}
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static int cpg_pll_clk_determine_rate(struct clk_hw *hw,
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struct clk_rate_request *req)
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{
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unsigned int min_mult, max_mult, mult;
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unsigned long prate;
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prate = req->best_parent_rate * 2;
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min_mult = max(div64_ul(req->min_rate, prate), 1ULL);
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max_mult = min(div64_ul(req->max_rate, prate), 256ULL);
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if (max_mult < min_mult)
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return -EINVAL;
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mult = DIV_ROUND_CLOSEST_ULL(req->rate, prate);
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mult = clamp(mult, min_mult, max_mult);
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req->rate = prate * mult;
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return 0;
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}
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static int cpg_pll_clk_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct cpg_pll_clk *pll_clk = to_pll_clk(hw);
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unsigned int mult;
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u32 val;
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mult = DIV_ROUND_CLOSEST_ULL(rate, parent_rate * 2);
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mult = clamp(mult, 1U, 256U);
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if (readl(pll_clk->pllcr0_reg) & CPG_PLLxCR0_KICK)
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return -EBUSY;
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cpg_reg_modify(pll_clk->pllcr0_reg, CPG_PLLxCR0_NI,
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FIELD_PREP(CPG_PLLxCR0_NI, mult - 1));
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/*
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* Set KICK bit in PLLxCR0 to update hardware setting and wait for
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* clock change completion.
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*/
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cpg_reg_modify(pll_clk->pllcr0_reg, 0, CPG_PLLxCR0_KICK);
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/*
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* Note: There is no HW information about the worst case latency.
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*
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* Using experimental measurements, it seems that no more than
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* ~45 µs are needed, independently of the CPU rate.
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* Since this value might be dependent on external xtal rate, pll
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* rate or even the other emulation clocks rate, use 1000 as a
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* "super" safe value.
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*/
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return readl_poll_timeout(pll_clk->pllecr_reg, val,
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val & pll_clk->pllecr_pllst_mask, 0, 1000);
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}
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static const struct clk_ops cpg_pll_clk_ops = {
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.recalc_rate = cpg_pll_clk_recalc_rate,
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.determine_rate = cpg_pll_clk_determine_rate,
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.set_rate = cpg_pll_clk_set_rate,
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};
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static struct clk * __init cpg_pll_clk_register(const char *name,
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const char *parent_name,
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void __iomem *base,
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unsigned int cr0_offset,
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unsigned int cr1_offset,
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unsigned int index)
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{
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struct cpg_pll_clk *pll_clk;
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struct clk_init_data init = {};
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struct clk *clk;
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pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL);
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if (!pll_clk)
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return ERR_PTR(-ENOMEM);
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init.name = name;
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init.ops = &cpg_pll_clk_ops;
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init.parent_names = &parent_name;
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init.num_parents = 1;
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pll_clk->hw.init = &init;
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pll_clk->pllcr0_reg = base + cr0_offset;
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pll_clk->pllecr_reg = base + CPG_PLLECR;
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pll_clk->pllecr_pllst_mask = CPG_PLLECR_PLLST(index);
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/* Disable Fractional Multiplication and Frequency Dithering */
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writel(0, base + cr1_offset);
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cpg_reg_modify(pll_clk->pllcr0_reg, CPG_PLLxCR0_SSMODE, 0);
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clk = clk_register(NULL, &pll_clk->hw);
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if (IS_ERR(clk))
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kfree(pll_clk);
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return clk;
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}
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/*
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* Z0 Clock & Z1 Clock
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*/
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#define CPG_FRQCRB 0x00000804
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#define CPG_FRQCRB_KICK BIT(31)
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#define CPG_FRQCRC 0x00000808
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struct cpg_z_clk {
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struct clk_hw hw;
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void __iomem *reg;
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void __iomem *kick_reg;
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unsigned long max_rate; /* Maximum rate for normal mode */
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unsigned int fixed_div;
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u32 mask;
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};
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#define to_z_clk(_hw) container_of(_hw, struct cpg_z_clk, hw)
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static unsigned long cpg_z_clk_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct cpg_z_clk *zclk = to_z_clk(hw);
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unsigned int mult;
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u32 val;
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val = readl(zclk->reg) & zclk->mask;
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mult = 32 - (val >> __ffs(zclk->mask));
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return DIV_ROUND_CLOSEST_ULL((u64)parent_rate * mult,
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32 * zclk->fixed_div);
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}
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static int cpg_z_clk_determine_rate(struct clk_hw *hw,
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struct clk_rate_request *req)
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{
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struct cpg_z_clk *zclk = to_z_clk(hw);
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unsigned int min_mult, max_mult, mult;
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unsigned long rate, prate;
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rate = min(req->rate, req->max_rate);
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if (rate <= zclk->max_rate) {
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/* Set parent rate to initial value for normal modes */
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prate = zclk->max_rate;
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} else {
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/* Set increased parent rate for boost modes */
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prate = rate;
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}
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req->best_parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw),
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prate * zclk->fixed_div);
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prate = req->best_parent_rate / zclk->fixed_div;
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min_mult = max(div64_ul(req->min_rate * 32ULL, prate), 1ULL);
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max_mult = min(div64_ul(req->max_rate * 32ULL, prate), 32ULL);
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if (max_mult < min_mult)
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return -EINVAL;
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mult = DIV_ROUND_CLOSEST_ULL(rate * 32ULL, prate);
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mult = clamp(mult, min_mult, max_mult);
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req->rate = DIV_ROUND_CLOSEST_ULL((u64)prate * mult, 32);
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return 0;
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}
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static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct cpg_z_clk *zclk = to_z_clk(hw);
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unsigned int mult;
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unsigned int i;
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mult = DIV64_U64_ROUND_CLOSEST(rate * 32ULL * zclk->fixed_div,
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parent_rate);
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mult = clamp(mult, 1U, 32U);
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if (readl(zclk->kick_reg) & CPG_FRQCRB_KICK)
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return -EBUSY;
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cpg_reg_modify(zclk->reg, zclk->mask, (32 - mult) << __ffs(zclk->mask));
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/*
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* Set KICK bit in FRQCRB to update hardware setting and wait for
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* clock change completion.
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*/
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cpg_reg_modify(zclk->kick_reg, 0, CPG_FRQCRB_KICK);
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/*
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* Note: There is no HW information about the worst case latency.
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*
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* Using experimental measurements, it seems that no more than
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* ~10 iterations are needed, independently of the CPU rate.
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* Since this value might be dependent on external xtal rate, pll1
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* rate or even the other emulation clocks rate, use 1000 as a
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* "super" safe value.
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*/
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for (i = 1000; i; i--) {
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if (!(readl(zclk->kick_reg) & CPG_FRQCRB_KICK))
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return 0;
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cpu_relax();
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}
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return -ETIMEDOUT;
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}
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static const struct clk_ops cpg_z_clk_ops = {
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.recalc_rate = cpg_z_clk_recalc_rate,
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.determine_rate = cpg_z_clk_determine_rate,
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.set_rate = cpg_z_clk_set_rate,
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};
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static struct clk * __init cpg_z_clk_register(const char *name,
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const char *parent_name,
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void __iomem *reg,
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unsigned int div,
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unsigned int offset)
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{
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struct clk_init_data init = {};
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struct cpg_z_clk *zclk;
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struct clk *clk;
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zclk = kzalloc(sizeof(*zclk), GFP_KERNEL);
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if (!zclk)
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return ERR_PTR(-ENOMEM);
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init.name = name;
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init.ops = &cpg_z_clk_ops;
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init.flags = CLK_SET_RATE_PARENT;
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init.parent_names = &parent_name;
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init.num_parents = 1;
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zclk->reg = reg + CPG_FRQCRC;
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zclk->kick_reg = reg + CPG_FRQCRB;
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zclk->hw.init = &init;
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zclk->mask = GENMASK(offset + 4, offset);
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zclk->fixed_div = div; /* PLLVCO x 1/div x SYS-CPU divider */
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clk = clk_register(NULL, &zclk->hw);
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if (IS_ERR(clk)) {
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kfree(zclk);
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return clk;
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}
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zclk->max_rate = clk_hw_get_rate(clk_hw_get_parent(&zclk->hw)) /
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zclk->fixed_div;
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return clk;
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}
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/*
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* RPC Clocks
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*/
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static const struct clk_div_table cpg_rpcsrc_div_table[] = {
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{ 0, 4 }, { 1, 6 }, { 2, 5 }, { 3, 6 }, { 0, 0 },
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};
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struct clk * __init rcar_gen4_cpg_clk_register(struct device *dev,
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const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
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struct clk **clks, void __iomem *base,
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struct raw_notifier_head *notifiers)
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{
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const struct clk *parent;
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unsigned int mult = 1;
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unsigned int div = 1;
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u32 value;
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parent = clks[core->parent & 0xffff]; /* some types use high bits */
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if (IS_ERR(parent))
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return ERR_CAST(parent);
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switch (core->type) {
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case CLK_TYPE_GEN4_MAIN:
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div = cpg_pll_config->extal_div;
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break;
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case CLK_TYPE_GEN4_PLL1:
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mult = cpg_pll_config->pll1_mult;
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div = cpg_pll_config->pll1_div;
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break;
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case CLK_TYPE_GEN4_PLL2_VAR:
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/*
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* PLL2 is implemented as a custom clock, to change the
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* multiplier when cpufreq changes between normal and boost
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* modes.
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*/
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return cpg_pll_clk_register(core->name, __clk_get_name(parent),
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base, CPG_PLL2CR0, CPG_PLL2CR1, 2);
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case CLK_TYPE_GEN4_PLL2:
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mult = cpg_pll_config->pll2_mult;
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div = cpg_pll_config->pll2_div;
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break;
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case CLK_TYPE_GEN4_PLL3:
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mult = cpg_pll_config->pll3_mult;
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div = cpg_pll_config->pll3_div;
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break;
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case CLK_TYPE_GEN4_PLL4:
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mult = cpg_pll_config->pll4_mult;
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div = cpg_pll_config->pll4_div;
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break;
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case CLK_TYPE_GEN4_PLL5:
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mult = cpg_pll_config->pll5_mult;
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div = cpg_pll_config->pll5_div;
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break;
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case CLK_TYPE_GEN4_PLL6:
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mult = cpg_pll_config->pll6_mult;
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div = cpg_pll_config->pll6_div;
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break;
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case CLK_TYPE_GEN4_PLL2X_3X:
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value = readl(base + core->offset);
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mult = (((value >> 24) & 0x7f) + 1) * 2;
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break;
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case CLK_TYPE_GEN4_Z:
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return cpg_z_clk_register(core->name, __clk_get_name(parent),
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base, core->div, core->offset);
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case CLK_TYPE_GEN4_SDSRC:
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div = ((readl(base + SD0CKCR1) >> 29) & 0x03) + 4;
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break;
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case CLK_TYPE_GEN4_SDH:
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return cpg_sdh_clk_register(core->name, base + core->offset,
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__clk_get_name(parent), notifiers);
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case CLK_TYPE_GEN4_SD:
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return cpg_sd_clk_register(core->name, base + core->offset,
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__clk_get_name(parent));
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case CLK_TYPE_GEN4_MDSEL:
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/*
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* Clock selectable between two parents and two fixed dividers
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* using a mode pin
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*/
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if (cpg_mode & BIT(core->offset)) {
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div = core->div & 0xffff;
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} else {
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parent = clks[core->parent >> 16];
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if (IS_ERR(parent))
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return ERR_CAST(parent);
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div = core->div >> 16;
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}
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mult = 1;
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break;
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case CLK_TYPE_GEN4_OSC:
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/*
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* Clock combining OSC EXTAL predivider and a fixed divider
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*/
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div = cpg_pll_config->osc_prediv * core->div;
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break;
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case CLK_TYPE_GEN4_RPCSRC:
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return clk_register_divider_table(NULL, core->name,
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__clk_get_name(parent), 0,
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base + CPG_RPCCKCR, 3, 2, 0,
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cpg_rpcsrc_div_table,
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&cpg_lock);
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case CLK_TYPE_GEN4_RPC:
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return cpg_rpc_clk_register(core->name, base + CPG_RPCCKCR,
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__clk_get_name(parent), notifiers);
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case CLK_TYPE_GEN4_RPCD2:
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return cpg_rpcd2_clk_register(core->name, base + CPG_RPCCKCR,
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__clk_get_name(parent));
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default:
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return ERR_PTR(-EINVAL);
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}
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return clk_register_fixed_factor(NULL, core->name,
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__clk_get_name(parent), 0, mult, div);
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}
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int __init rcar_gen4_cpg_init(const struct rcar_gen4_cpg_pll_config *config,
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unsigned int clk_extalr, u32 mode)
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{
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cpg_pll_config = config;
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cpg_clk_extalr = clk_extalr;
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cpg_mode = mode;
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spin_lock_init(&cpg_lock);
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return 0;
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}
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