438 lines
10 KiB
C
438 lines
10 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/* Copyright (C) 2020 Marvell. */
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#include "otx2_cpt_common.h"
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#include "otx2_cptvf.h"
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#include "otx2_cptlf.h"
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#include "otx2_cptvf_algs.h"
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#include "cn10k_cpt.h"
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#include <rvu_reg.h>
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#define OTX2_CPTVF_DRV_NAME "rvu_cptvf"
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static void cptvf_enable_pfvf_mbox_intrs(struct otx2_cptvf_dev *cptvf)
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{
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/* Clear interrupt if any */
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otx2_cpt_write64(cptvf->reg_base, BLKADDR_RVUM, 0, OTX2_RVU_VF_INT,
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0x1ULL);
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/* Enable PF-VF interrupt */
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otx2_cpt_write64(cptvf->reg_base, BLKADDR_RVUM, 0,
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OTX2_RVU_VF_INT_ENA_W1S, 0x1ULL);
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}
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static void cptvf_disable_pfvf_mbox_intrs(struct otx2_cptvf_dev *cptvf)
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{
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/* Disable PF-VF interrupt */
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otx2_cpt_write64(cptvf->reg_base, BLKADDR_RVUM, 0,
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OTX2_RVU_VF_INT_ENA_W1C, 0x1ULL);
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/* Clear interrupt if any */
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otx2_cpt_write64(cptvf->reg_base, BLKADDR_RVUM, 0, OTX2_RVU_VF_INT,
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0x1ULL);
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}
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static int cptvf_register_interrupts(struct otx2_cptvf_dev *cptvf)
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{
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int ret, irq;
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int num_vec;
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num_vec = pci_msix_vec_count(cptvf->pdev);
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if (num_vec <= 0)
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return -EINVAL;
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/* Enable MSI-X */
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ret = pci_alloc_irq_vectors(cptvf->pdev, num_vec, num_vec,
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PCI_IRQ_MSIX);
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if (ret < 0) {
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dev_err(&cptvf->pdev->dev,
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"Request for %d msix vectors failed\n", num_vec);
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return ret;
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}
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irq = pci_irq_vector(cptvf->pdev, OTX2_CPT_VF_INT_VEC_E_MBOX);
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/* Register VF<=>PF mailbox interrupt handler */
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ret = devm_request_irq(&cptvf->pdev->dev, irq,
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otx2_cptvf_pfvf_mbox_intr, 0,
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"CPTPFVF Mbox", cptvf);
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if (ret)
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return ret;
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/* Enable PF-VF mailbox interrupts */
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cptvf_enable_pfvf_mbox_intrs(cptvf);
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ret = otx2_cpt_send_ready_msg(&cptvf->pfvf_mbox, cptvf->pdev);
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if (ret) {
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dev_warn(&cptvf->pdev->dev,
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"PF not responding to mailbox, deferring probe\n");
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cptvf_disable_pfvf_mbox_intrs(cptvf);
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return -EPROBE_DEFER;
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}
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return 0;
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}
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static int cptvf_pfvf_mbox_init(struct otx2_cptvf_dev *cptvf)
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{
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struct pci_dev *pdev = cptvf->pdev;
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resource_size_t offset, size;
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int ret;
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cptvf->pfvf_mbox_wq = alloc_workqueue("cpt_pfvf_mailbox",
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WQ_UNBOUND | WQ_HIGHPRI |
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WQ_MEM_RECLAIM, 1);
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if (!cptvf->pfvf_mbox_wq)
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return -ENOMEM;
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if (test_bit(CN10K_MBOX, &cptvf->cap_flag)) {
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/* For cn10k platform, VF mailbox region is in its BAR2
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* register space
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*/
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cptvf->pfvf_mbox_base = cptvf->reg_base +
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CN10K_CPT_VF_MBOX_REGION;
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} else {
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offset = pci_resource_start(pdev, PCI_MBOX_BAR_NUM);
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size = pci_resource_len(pdev, PCI_MBOX_BAR_NUM);
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/* Map PF-VF mailbox memory */
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cptvf->pfvf_mbox_base = devm_ioremap_wc(&pdev->dev, offset,
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size);
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if (!cptvf->pfvf_mbox_base) {
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dev_err(&pdev->dev, "Unable to map BAR4\n");
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ret = -ENOMEM;
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goto free_wqe;
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}
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}
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ret = otx2_mbox_init(&cptvf->pfvf_mbox, cptvf->pfvf_mbox_base,
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pdev, cptvf->reg_base, MBOX_DIR_VFPF, 1);
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if (ret)
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goto free_wqe;
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ret = otx2_cpt_mbox_bbuf_init(cptvf, pdev);
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if (ret)
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goto destroy_mbox;
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INIT_WORK(&cptvf->pfvf_mbox_work, otx2_cptvf_pfvf_mbox_handler);
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return 0;
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destroy_mbox:
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otx2_mbox_destroy(&cptvf->pfvf_mbox);
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free_wqe:
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destroy_workqueue(cptvf->pfvf_mbox_wq);
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return ret;
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}
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static void cptvf_pfvf_mbox_destroy(struct otx2_cptvf_dev *cptvf)
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{
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destroy_workqueue(cptvf->pfvf_mbox_wq);
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otx2_mbox_destroy(&cptvf->pfvf_mbox);
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}
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static void cptlf_work_handler(unsigned long data)
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{
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otx2_cpt_post_process((struct otx2_cptlf_wqe *) data);
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}
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static void cleanup_tasklet_work(struct otx2_cptlfs_info *lfs)
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{
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int i;
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for (i = 0; i < lfs->lfs_num; i++) {
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if (!lfs->lf[i].wqe)
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continue;
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tasklet_kill(&lfs->lf[i].wqe->work);
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kfree(lfs->lf[i].wqe);
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lfs->lf[i].wqe = NULL;
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}
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}
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static int init_tasklet_work(struct otx2_cptlfs_info *lfs)
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{
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struct otx2_cptlf_wqe *wqe;
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int i, ret = 0;
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for (i = 0; i < lfs->lfs_num; i++) {
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wqe = kzalloc(sizeof(struct otx2_cptlf_wqe), GFP_KERNEL);
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if (!wqe) {
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ret = -ENOMEM;
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goto cleanup_tasklet;
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}
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tasklet_init(&wqe->work, cptlf_work_handler, (u64) wqe);
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wqe->lfs = lfs;
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wqe->lf_num = i;
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lfs->lf[i].wqe = wqe;
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}
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return 0;
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cleanup_tasklet:
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cleanup_tasklet_work(lfs);
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return ret;
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}
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static void free_pending_queues(struct otx2_cptlfs_info *lfs)
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{
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int i;
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for (i = 0; i < lfs->lfs_num; i++) {
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kfree(lfs->lf[i].pqueue.head);
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lfs->lf[i].pqueue.head = NULL;
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}
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}
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static int alloc_pending_queues(struct otx2_cptlfs_info *lfs)
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{
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int size, ret, i;
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if (!lfs->lfs_num)
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return -EINVAL;
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for (i = 0; i < lfs->lfs_num; i++) {
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lfs->lf[i].pqueue.qlen = OTX2_CPT_INST_QLEN_MSGS;
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size = lfs->lf[i].pqueue.qlen *
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sizeof(struct otx2_cpt_pending_entry);
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lfs->lf[i].pqueue.head = kzalloc(size, GFP_KERNEL);
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if (!lfs->lf[i].pqueue.head) {
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ret = -ENOMEM;
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goto error;
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}
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/* Initialize spin lock */
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spin_lock_init(&lfs->lf[i].pqueue.lock);
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}
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return 0;
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error:
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free_pending_queues(lfs);
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return ret;
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}
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static void lf_sw_cleanup(struct otx2_cptlfs_info *lfs)
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{
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cleanup_tasklet_work(lfs);
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free_pending_queues(lfs);
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}
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static int lf_sw_init(struct otx2_cptlfs_info *lfs)
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{
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int ret;
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ret = alloc_pending_queues(lfs);
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if (ret) {
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dev_err(&lfs->pdev->dev,
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"Allocating pending queues failed\n");
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return ret;
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}
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ret = init_tasklet_work(lfs);
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if (ret) {
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dev_err(&lfs->pdev->dev,
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"Tasklet work init failed\n");
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goto pending_queues_free;
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}
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return 0;
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pending_queues_free:
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free_pending_queues(lfs);
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return ret;
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}
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static void cptvf_lf_shutdown(struct otx2_cptlfs_info *lfs)
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{
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atomic_set(&lfs->state, OTX2_CPTLF_IN_RESET);
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/* Remove interrupts affinity */
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otx2_cptlf_free_irqs_affinity(lfs);
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/* Disable instruction queue */
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otx2_cptlf_disable_iqueues(lfs);
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/* Unregister crypto algorithms */
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otx2_cpt_crypto_exit(lfs->pdev, THIS_MODULE);
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/* Unregister LFs interrupts */
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otx2_cptlf_unregister_interrupts(lfs);
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/* Cleanup LFs software side */
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lf_sw_cleanup(lfs);
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/* Send request to detach LFs */
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otx2_cpt_detach_rsrcs_msg(lfs);
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}
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static int cptvf_lf_init(struct otx2_cptvf_dev *cptvf)
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{
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struct otx2_cptlfs_info *lfs = &cptvf->lfs;
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struct device *dev = &cptvf->pdev->dev;
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int ret, lfs_num;
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u8 eng_grp_msk;
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/* Get engine group number for symmetric crypto */
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cptvf->lfs.kcrypto_eng_grp_num = OTX2_CPT_INVALID_CRYPTO_ENG_GRP;
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ret = otx2_cptvf_send_eng_grp_num_msg(cptvf, OTX2_CPT_SE_TYPES);
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if (ret)
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return ret;
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if (cptvf->lfs.kcrypto_eng_grp_num == OTX2_CPT_INVALID_CRYPTO_ENG_GRP) {
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dev_err(dev, "Engine group for kernel crypto not available\n");
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ret = -ENOENT;
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return ret;
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}
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eng_grp_msk = 1 << cptvf->lfs.kcrypto_eng_grp_num;
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ret = otx2_cptvf_send_kvf_limits_msg(cptvf);
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if (ret)
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return ret;
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lfs->reg_base = cptvf->reg_base;
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lfs->pdev = cptvf->pdev;
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lfs->mbox = &cptvf->pfvf_mbox;
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lfs_num = cptvf->lfs.kvf_limits ? cptvf->lfs.kvf_limits :
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num_online_cpus();
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ret = otx2_cptlf_init(lfs, eng_grp_msk, OTX2_CPT_QUEUE_HI_PRIO,
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lfs_num);
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if (ret)
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return ret;
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/* Get msix offsets for attached LFs */
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ret = otx2_cpt_msix_offset_msg(lfs);
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if (ret)
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goto cleanup_lf;
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/* Initialize LFs software side */
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ret = lf_sw_init(lfs);
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if (ret)
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goto cleanup_lf;
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/* Register LFs interrupts */
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ret = otx2_cptlf_register_interrupts(lfs);
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if (ret)
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goto cleanup_lf_sw;
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/* Set interrupts affinity */
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ret = otx2_cptlf_set_irqs_affinity(lfs);
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if (ret)
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goto unregister_intr;
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atomic_set(&lfs->state, OTX2_CPTLF_STARTED);
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/* Register crypto algorithms */
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ret = otx2_cpt_crypto_init(lfs->pdev, THIS_MODULE, lfs_num, 1);
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if (ret) {
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dev_err(&lfs->pdev->dev, "algorithms registration failed\n");
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goto disable_irqs;
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}
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return 0;
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disable_irqs:
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otx2_cptlf_free_irqs_affinity(lfs);
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unregister_intr:
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otx2_cptlf_unregister_interrupts(lfs);
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cleanup_lf_sw:
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lf_sw_cleanup(lfs);
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cleanup_lf:
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otx2_cptlf_shutdown(lfs);
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return ret;
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}
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static int otx2_cptvf_probe(struct pci_dev *pdev,
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const struct pci_device_id *ent)
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{
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struct device *dev = &pdev->dev;
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struct otx2_cptvf_dev *cptvf;
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int ret;
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cptvf = devm_kzalloc(dev, sizeof(*cptvf), GFP_KERNEL);
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if (!cptvf)
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return -ENOMEM;
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ret = pcim_enable_device(pdev);
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if (ret) {
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dev_err(dev, "Failed to enable PCI device\n");
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goto clear_drvdata;
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}
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ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48));
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if (ret) {
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dev_err(dev, "Unable to get usable DMA configuration\n");
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goto clear_drvdata;
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}
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/* Map VF's configuration registers */
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ret = pcim_iomap_regions_request_all(pdev, 1 << PCI_PF_REG_BAR_NUM,
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OTX2_CPTVF_DRV_NAME);
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if (ret) {
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dev_err(dev, "Couldn't get PCI resources 0x%x\n", ret);
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goto clear_drvdata;
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}
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pci_set_master(pdev);
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pci_set_drvdata(pdev, cptvf);
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cptvf->pdev = pdev;
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cptvf->reg_base = pcim_iomap_table(pdev)[PCI_PF_REG_BAR_NUM];
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otx2_cpt_set_hw_caps(pdev, &cptvf->cap_flag);
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ret = cn10k_cptvf_lmtst_init(cptvf);
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if (ret)
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goto clear_drvdata;
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/* Initialize PF<=>VF mailbox */
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ret = cptvf_pfvf_mbox_init(cptvf);
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if (ret)
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goto clear_drvdata;
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/* Register interrupts */
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ret = cptvf_register_interrupts(cptvf);
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if (ret)
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goto destroy_pfvf_mbox;
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/* Initialize CPT LFs */
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ret = cptvf_lf_init(cptvf);
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if (ret)
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goto unregister_interrupts;
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return 0;
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unregister_interrupts:
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cptvf_disable_pfvf_mbox_intrs(cptvf);
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destroy_pfvf_mbox:
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cptvf_pfvf_mbox_destroy(cptvf);
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clear_drvdata:
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pci_set_drvdata(pdev, NULL);
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return ret;
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}
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static void otx2_cptvf_remove(struct pci_dev *pdev)
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{
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struct otx2_cptvf_dev *cptvf = pci_get_drvdata(pdev);
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if (!cptvf) {
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dev_err(&pdev->dev, "Invalid CPT VF device.\n");
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return;
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}
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cptvf_lf_shutdown(&cptvf->lfs);
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/* Disable PF-VF mailbox interrupt */
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cptvf_disable_pfvf_mbox_intrs(cptvf);
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/* Destroy PF-VF mbox */
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cptvf_pfvf_mbox_destroy(cptvf);
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pci_set_drvdata(pdev, NULL);
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}
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/* Supported devices */
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static const struct pci_device_id otx2_cptvf_id_table[] = {
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{PCI_VDEVICE(CAVIUM, OTX2_CPT_PCI_VF_DEVICE_ID), 0},
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{PCI_VDEVICE(CAVIUM, CN10K_CPT_PCI_VF_DEVICE_ID), 0},
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{ 0, } /* end of table */
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};
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static struct pci_driver otx2_cptvf_pci_driver = {
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.name = OTX2_CPTVF_DRV_NAME,
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.id_table = otx2_cptvf_id_table,
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.probe = otx2_cptvf_probe,
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.remove = otx2_cptvf_remove,
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};
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module_pci_driver(otx2_cptvf_pci_driver);
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MODULE_IMPORT_NS(CRYPTO_DEV_OCTEONTX2_CPT);
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MODULE_AUTHOR("Marvell");
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MODULE_DESCRIPTION("Marvell RVU CPT Virtual Function Driver");
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MODULE_LICENSE("GPL v2");
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MODULE_DEVICE_TABLE(pci, otx2_cptvf_id_table);
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