591 lines
17 KiB
C
591 lines
17 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* GPIO driver for the ACCES PCIe-IDIO-24 family
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* Copyright (C) 2018 William Breathitt Gray
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, version 2, as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* This driver supports the following ACCES devices: PCIe-IDIO-24,
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* PCIe-IDI-24, PCIe-IDO-24, and PCIe-IDIO-12.
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*/
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#include <linux/bitmap.h>
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#include <linux/bitops.h>
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#include <linux/device.h>
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#include <linux/errno.h>
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#include <linux/gpio/driver.h>
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#include <linux/interrupt.h>
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#include <linux/irqdesc.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/spinlock.h>
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#include <linux/types.h>
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/*
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* PLX PEX8311 PCI LCS_INTCSR Interrupt Control/Status
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*
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* Bit: Description
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* 0: Enable Interrupt Sources (Bit 0)
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* 1: Enable Interrupt Sources (Bit 1)
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* 2: Generate Internal PCI Bus Internal SERR# Interrupt
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* 3: Mailbox Interrupt Enable
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* 4: Power Management Interrupt Enable
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* 5: Power Management Interrupt
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* 6: Slave Read Local Data Parity Check Error Enable
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* 7: Slave Read Local Data Parity Check Error Status
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* 8: Internal PCI Wire Interrupt Enable
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* 9: PCI Express Doorbell Interrupt Enable
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* 10: PCI Abort Interrupt Enable
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* 11: Local Interrupt Input Enable
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* 12: Retry Abort Enable
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* 13: PCI Express Doorbell Interrupt Active
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* 14: PCI Abort Interrupt Active
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* 15: Local Interrupt Input Active
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* 16: Local Interrupt Output Enable
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* 17: Local Doorbell Interrupt Enable
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* 18: DMA Channel 0 Interrupt Enable
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* 19: DMA Channel 1 Interrupt Enable
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* 20: Local Doorbell Interrupt Active
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* 21: DMA Channel 0 Interrupt Active
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* 22: DMA Channel 1 Interrupt Active
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* 23: Built-In Self-Test (BIST) Interrupt Active
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* 24: Direct Master was the Bus Master during a Master or Target Abort
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* 25: DMA Channel 0 was the Bus Master during a Master or Target Abort
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* 26: DMA Channel 1 was the Bus Master during a Master or Target Abort
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* 27: Target Abort after internal 256 consecutive Master Retrys
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* 28: PCI Bus wrote data to LCS_MBOX0
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* 29: PCI Bus wrote data to LCS_MBOX1
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* 30: PCI Bus wrote data to LCS_MBOX2
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* 31: PCI Bus wrote data to LCS_MBOX3
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*/
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#define PLX_PEX8311_PCI_LCS_INTCSR 0x68
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#define INTCSR_INTERNAL_PCI_WIRE BIT(8)
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#define INTCSR_LOCAL_INPUT BIT(11)
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/**
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* struct idio_24_gpio_reg - GPIO device registers structure
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* @out0_7: Read: FET Outputs 0-7
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* Write: FET Outputs 0-7
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* @out8_15: Read: FET Outputs 8-15
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* Write: FET Outputs 8-15
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* @out16_23: Read: FET Outputs 16-23
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* Write: FET Outputs 16-23
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* @ttl_out0_7: Read: TTL/CMOS Outputs 0-7
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* Write: TTL/CMOS Outputs 0-7
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* @in0_7: Read: Isolated Inputs 0-7
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* Write: Reserved
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* @in8_15: Read: Isolated Inputs 8-15
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* Write: Reserved
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* @in16_23: Read: Isolated Inputs 16-23
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* Write: Reserved
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* @ttl_in0_7: Read: TTL/CMOS Inputs 0-7
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* Write: Reserved
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* @cos0_7: Read: COS Status Inputs 0-7
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* Write: COS Clear Inputs 0-7
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* @cos8_15: Read: COS Status Inputs 8-15
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* Write: COS Clear Inputs 8-15
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* @cos16_23: Read: COS Status Inputs 16-23
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* Write: COS Clear Inputs 16-23
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* @cos_ttl0_7: Read: COS Status TTL/CMOS 0-7
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* Write: COS Clear TTL/CMOS 0-7
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* @ctl: Read: Control Register
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* Write: Control Register
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* @reserved: Read: Reserved
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* Write: Reserved
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* @cos_enable: Read: COS Enable
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* Write: COS Enable
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* @soft_reset: Read: IRQ Output Pin Status
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* Write: Software Board Reset
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*/
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struct idio_24_gpio_reg {
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u8 out0_7;
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u8 out8_15;
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u8 out16_23;
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u8 ttl_out0_7;
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u8 in0_7;
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u8 in8_15;
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u8 in16_23;
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u8 ttl_in0_7;
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u8 cos0_7;
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u8 cos8_15;
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u8 cos16_23;
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u8 cos_ttl0_7;
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u8 ctl;
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u8 reserved;
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u8 cos_enable;
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u8 soft_reset;
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};
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/**
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* struct idio_24_gpio - GPIO device private data structure
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* @chip: instance of the gpio_chip
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* @lock: synchronization lock to prevent I/O race conditions
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* @reg: I/O address offset for the GPIO device registers
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* @irq_mask: I/O bits affected by interrupts
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*/
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struct idio_24_gpio {
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struct gpio_chip chip;
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raw_spinlock_t lock;
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__u8 __iomem *plx;
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struct idio_24_gpio_reg __iomem *reg;
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unsigned long irq_mask;
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};
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static int idio_24_gpio_get_direction(struct gpio_chip *chip,
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unsigned int offset)
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{
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struct idio_24_gpio *const idio24gpio = gpiochip_get_data(chip);
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const unsigned long out_mode_mask = BIT(1);
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/* FET Outputs */
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if (offset < 24)
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return GPIO_LINE_DIRECTION_OUT;
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/* Isolated Inputs */
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if (offset < 48)
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return GPIO_LINE_DIRECTION_IN;
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/* TTL/CMOS I/O */
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/* OUT MODE = 1 when TTL/CMOS Output Mode is set */
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if (ioread8(&idio24gpio->reg->ctl) & out_mode_mask)
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return GPIO_LINE_DIRECTION_OUT;
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return GPIO_LINE_DIRECTION_IN;
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}
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static int idio_24_gpio_direction_input(struct gpio_chip *chip,
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unsigned int offset)
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{
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struct idio_24_gpio *const idio24gpio = gpiochip_get_data(chip);
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unsigned long flags;
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unsigned int ctl_state;
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const unsigned long out_mode_mask = BIT(1);
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/* TTL/CMOS I/O */
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if (offset > 47) {
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raw_spin_lock_irqsave(&idio24gpio->lock, flags);
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/* Clear TTL/CMOS Output Mode */
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ctl_state = ioread8(&idio24gpio->reg->ctl) & ~out_mode_mask;
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iowrite8(ctl_state, &idio24gpio->reg->ctl);
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raw_spin_unlock_irqrestore(&idio24gpio->lock, flags);
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}
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return 0;
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}
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static int idio_24_gpio_direction_output(struct gpio_chip *chip,
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unsigned int offset, int value)
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{
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struct idio_24_gpio *const idio24gpio = gpiochip_get_data(chip);
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unsigned long flags;
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unsigned int ctl_state;
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const unsigned long out_mode_mask = BIT(1);
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/* TTL/CMOS I/O */
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if (offset > 47) {
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raw_spin_lock_irqsave(&idio24gpio->lock, flags);
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/* Set TTL/CMOS Output Mode */
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ctl_state = ioread8(&idio24gpio->reg->ctl) | out_mode_mask;
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iowrite8(ctl_state, &idio24gpio->reg->ctl);
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raw_spin_unlock_irqrestore(&idio24gpio->lock, flags);
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}
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chip->set(chip, offset, value);
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return 0;
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}
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static int idio_24_gpio_get(struct gpio_chip *chip, unsigned int offset)
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{
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struct idio_24_gpio *const idio24gpio = gpiochip_get_data(chip);
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const unsigned long offset_mask = BIT(offset % 8);
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const unsigned long out_mode_mask = BIT(1);
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/* FET Outputs */
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if (offset < 8)
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return !!(ioread8(&idio24gpio->reg->out0_7) & offset_mask);
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if (offset < 16)
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return !!(ioread8(&idio24gpio->reg->out8_15) & offset_mask);
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if (offset < 24)
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return !!(ioread8(&idio24gpio->reg->out16_23) & offset_mask);
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/* Isolated Inputs */
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if (offset < 32)
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return !!(ioread8(&idio24gpio->reg->in0_7) & offset_mask);
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if (offset < 40)
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return !!(ioread8(&idio24gpio->reg->in8_15) & offset_mask);
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if (offset < 48)
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return !!(ioread8(&idio24gpio->reg->in16_23) & offset_mask);
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/* TTL/CMOS Outputs */
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if (ioread8(&idio24gpio->reg->ctl) & out_mode_mask)
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return !!(ioread8(&idio24gpio->reg->ttl_out0_7) & offset_mask);
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/* TTL/CMOS Inputs */
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return !!(ioread8(&idio24gpio->reg->ttl_in0_7) & offset_mask);
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}
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static int idio_24_gpio_get_multiple(struct gpio_chip *chip,
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unsigned long *mask, unsigned long *bits)
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{
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struct idio_24_gpio *const idio24gpio = gpiochip_get_data(chip);
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unsigned long offset;
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unsigned long gpio_mask;
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void __iomem *ports[] = {
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&idio24gpio->reg->out0_7, &idio24gpio->reg->out8_15,
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&idio24gpio->reg->out16_23, &idio24gpio->reg->in0_7,
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&idio24gpio->reg->in8_15, &idio24gpio->reg->in16_23,
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};
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size_t index;
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unsigned long port_state;
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const unsigned long out_mode_mask = BIT(1);
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/* clear bits array to a clean slate */
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bitmap_zero(bits, chip->ngpio);
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for_each_set_clump8(offset, gpio_mask, mask, ARRAY_SIZE(ports) * 8) {
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index = offset / 8;
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/* read bits from current gpio port (port 6 is TTL GPIO) */
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if (index < 6)
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port_state = ioread8(ports[index]);
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else if (ioread8(&idio24gpio->reg->ctl) & out_mode_mask)
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port_state = ioread8(&idio24gpio->reg->ttl_out0_7);
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else
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port_state = ioread8(&idio24gpio->reg->ttl_in0_7);
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port_state &= gpio_mask;
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bitmap_set_value8(bits, port_state, offset);
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}
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return 0;
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}
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static void idio_24_gpio_set(struct gpio_chip *chip, unsigned int offset,
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int value)
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{
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struct idio_24_gpio *const idio24gpio = gpiochip_get_data(chip);
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const unsigned long out_mode_mask = BIT(1);
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void __iomem *base;
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const unsigned int mask = BIT(offset % 8);
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unsigned long flags;
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unsigned int out_state;
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/* Isolated Inputs */
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if (offset > 23 && offset < 48)
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return;
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/* TTL/CMOS Inputs */
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if (offset > 47 && !(ioread8(&idio24gpio->reg->ctl) & out_mode_mask))
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return;
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/* TTL/CMOS Outputs */
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if (offset > 47)
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base = &idio24gpio->reg->ttl_out0_7;
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/* FET Outputs */
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else if (offset > 15)
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base = &idio24gpio->reg->out16_23;
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else if (offset > 7)
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base = &idio24gpio->reg->out8_15;
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else
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base = &idio24gpio->reg->out0_7;
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raw_spin_lock_irqsave(&idio24gpio->lock, flags);
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if (value)
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out_state = ioread8(base) | mask;
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else
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out_state = ioread8(base) & ~mask;
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iowrite8(out_state, base);
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raw_spin_unlock_irqrestore(&idio24gpio->lock, flags);
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}
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static void idio_24_gpio_set_multiple(struct gpio_chip *chip,
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unsigned long *mask, unsigned long *bits)
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{
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struct idio_24_gpio *const idio24gpio = gpiochip_get_data(chip);
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unsigned long offset;
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unsigned long gpio_mask;
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void __iomem *ports[] = {
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&idio24gpio->reg->out0_7, &idio24gpio->reg->out8_15,
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&idio24gpio->reg->out16_23
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};
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size_t index;
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unsigned long bitmask;
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unsigned long flags;
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unsigned long out_state;
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const unsigned long out_mode_mask = BIT(1);
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for_each_set_clump8(offset, gpio_mask, mask, ARRAY_SIZE(ports) * 8) {
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index = offset / 8;
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bitmask = bitmap_get_value8(bits, offset) & gpio_mask;
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raw_spin_lock_irqsave(&idio24gpio->lock, flags);
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/* read bits from current gpio port (port 6 is TTL GPIO) */
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if (index < 6) {
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out_state = ioread8(ports[index]);
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} else if (ioread8(&idio24gpio->reg->ctl) & out_mode_mask) {
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out_state = ioread8(&idio24gpio->reg->ttl_out0_7);
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} else {
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/* skip TTL GPIO if set for input */
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raw_spin_unlock_irqrestore(&idio24gpio->lock, flags);
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continue;
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}
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/* set requested bit states */
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out_state &= ~gpio_mask;
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out_state |= bitmask;
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/* write bits for current gpio port (port 6 is TTL GPIO) */
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if (index < 6)
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iowrite8(out_state, ports[index]);
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else
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iowrite8(out_state, &idio24gpio->reg->ttl_out0_7);
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raw_spin_unlock_irqrestore(&idio24gpio->lock, flags);
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}
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}
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static void idio_24_irq_ack(struct irq_data *data)
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{
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}
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static void idio_24_irq_mask(struct irq_data *data)
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{
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struct gpio_chip *const chip = irq_data_get_irq_chip_data(data);
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struct idio_24_gpio *const idio24gpio = gpiochip_get_data(chip);
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unsigned long flags;
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const unsigned long bit_offset = irqd_to_hwirq(data) - 24;
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unsigned char new_irq_mask;
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const unsigned long bank_offset = bit_offset / 8;
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unsigned char cos_enable_state;
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raw_spin_lock_irqsave(&idio24gpio->lock, flags);
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idio24gpio->irq_mask &= ~BIT(bit_offset);
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new_irq_mask = idio24gpio->irq_mask >> bank_offset * 8;
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if (!new_irq_mask) {
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cos_enable_state = ioread8(&idio24gpio->reg->cos_enable);
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/* Disable Rising Edge detection */
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cos_enable_state &= ~BIT(bank_offset);
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/* Disable Falling Edge detection */
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cos_enable_state &= ~BIT(bank_offset + 4);
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iowrite8(cos_enable_state, &idio24gpio->reg->cos_enable);
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}
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raw_spin_unlock_irqrestore(&idio24gpio->lock, flags);
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}
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static void idio_24_irq_unmask(struct irq_data *data)
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{
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struct gpio_chip *const chip = irq_data_get_irq_chip_data(data);
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struct idio_24_gpio *const idio24gpio = gpiochip_get_data(chip);
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unsigned long flags;
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unsigned char prev_irq_mask;
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const unsigned long bit_offset = irqd_to_hwirq(data) - 24;
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const unsigned long bank_offset = bit_offset / 8;
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unsigned char cos_enable_state;
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raw_spin_lock_irqsave(&idio24gpio->lock, flags);
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prev_irq_mask = idio24gpio->irq_mask >> bank_offset * 8;
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idio24gpio->irq_mask |= BIT(bit_offset);
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if (!prev_irq_mask) {
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cos_enable_state = ioread8(&idio24gpio->reg->cos_enable);
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/* Enable Rising Edge detection */
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cos_enable_state |= BIT(bank_offset);
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/* Enable Falling Edge detection */
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cos_enable_state |= BIT(bank_offset + 4);
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iowrite8(cos_enable_state, &idio24gpio->reg->cos_enable);
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}
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raw_spin_unlock_irqrestore(&idio24gpio->lock, flags);
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}
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static int idio_24_irq_set_type(struct irq_data *data, unsigned int flow_type)
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{
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/* The only valid irq types are none and both-edges */
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if (flow_type != IRQ_TYPE_NONE &&
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(flow_type & IRQ_TYPE_EDGE_BOTH) != IRQ_TYPE_EDGE_BOTH)
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return -EINVAL;
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return 0;
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}
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static struct irq_chip idio_24_irqchip = {
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.name = "pcie-idio-24",
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.irq_ack = idio_24_irq_ack,
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.irq_mask = idio_24_irq_mask,
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.irq_unmask = idio_24_irq_unmask,
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.irq_set_type = idio_24_irq_set_type
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};
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static irqreturn_t idio_24_irq_handler(int irq, void *dev_id)
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{
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struct idio_24_gpio *const idio24gpio = dev_id;
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unsigned long irq_status;
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struct gpio_chip *const chip = &idio24gpio->chip;
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unsigned long irq_mask;
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int gpio;
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raw_spin_lock(&idio24gpio->lock);
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/* Read Change-Of-State status */
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irq_status = ioread32(&idio24gpio->reg->cos0_7);
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raw_spin_unlock(&idio24gpio->lock);
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/* Make sure our device generated IRQ */
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if (!irq_status)
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return IRQ_NONE;
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/* Handle only unmasked IRQ */
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irq_mask = idio24gpio->irq_mask & irq_status;
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for_each_set_bit(gpio, &irq_mask, chip->ngpio - 24)
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generic_handle_domain_irq(chip->irq.domain, gpio + 24);
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raw_spin_lock(&idio24gpio->lock);
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/* Clear Change-Of-State status */
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iowrite32(irq_status, &idio24gpio->reg->cos0_7);
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raw_spin_unlock(&idio24gpio->lock);
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return IRQ_HANDLED;
|
|
}
|
|
|
|
#define IDIO_24_NGPIO 56
|
|
static const char *idio_24_names[IDIO_24_NGPIO] = {
|
|
"OUT0", "OUT1", "OUT2", "OUT3", "OUT4", "OUT5", "OUT6", "OUT7",
|
|
"OUT8", "OUT9", "OUT10", "OUT11", "OUT12", "OUT13", "OUT14", "OUT15",
|
|
"OUT16", "OUT17", "OUT18", "OUT19", "OUT20", "OUT21", "OUT22", "OUT23",
|
|
"IIN0", "IIN1", "IIN2", "IIN3", "IIN4", "IIN5", "IIN6", "IIN7",
|
|
"IIN8", "IIN9", "IIN10", "IIN11", "IIN12", "IIN13", "IIN14", "IIN15",
|
|
"IIN16", "IIN17", "IIN18", "IIN19", "IIN20", "IIN21", "IIN22", "IIN23",
|
|
"TTL0", "TTL1", "TTL2", "TTL3", "TTL4", "TTL5", "TTL6", "TTL7"
|
|
};
|
|
|
|
static int idio_24_probe(struct pci_dev *pdev, const struct pci_device_id *id)
|
|
{
|
|
struct device *const dev = &pdev->dev;
|
|
struct idio_24_gpio *idio24gpio;
|
|
int err;
|
|
const size_t pci_plx_bar_index = 1;
|
|
const size_t pci_bar_index = 2;
|
|
const char *const name = pci_name(pdev);
|
|
struct gpio_irq_chip *girq;
|
|
|
|
idio24gpio = devm_kzalloc(dev, sizeof(*idio24gpio), GFP_KERNEL);
|
|
if (!idio24gpio)
|
|
return -ENOMEM;
|
|
|
|
err = pcim_enable_device(pdev);
|
|
if (err) {
|
|
dev_err(dev, "Failed to enable PCI device (%d)\n", err);
|
|
return err;
|
|
}
|
|
|
|
err = pcim_iomap_regions(pdev, BIT(pci_plx_bar_index) | BIT(pci_bar_index), name);
|
|
if (err) {
|
|
dev_err(dev, "Unable to map PCI I/O addresses (%d)\n", err);
|
|
return err;
|
|
}
|
|
|
|
idio24gpio->plx = pcim_iomap_table(pdev)[pci_plx_bar_index];
|
|
idio24gpio->reg = pcim_iomap_table(pdev)[pci_bar_index];
|
|
|
|
idio24gpio->chip.label = name;
|
|
idio24gpio->chip.parent = dev;
|
|
idio24gpio->chip.owner = THIS_MODULE;
|
|
idio24gpio->chip.base = -1;
|
|
idio24gpio->chip.ngpio = IDIO_24_NGPIO;
|
|
idio24gpio->chip.names = idio_24_names;
|
|
idio24gpio->chip.get_direction = idio_24_gpio_get_direction;
|
|
idio24gpio->chip.direction_input = idio_24_gpio_direction_input;
|
|
idio24gpio->chip.direction_output = idio_24_gpio_direction_output;
|
|
idio24gpio->chip.get = idio_24_gpio_get;
|
|
idio24gpio->chip.get_multiple = idio_24_gpio_get_multiple;
|
|
idio24gpio->chip.set = idio_24_gpio_set;
|
|
idio24gpio->chip.set_multiple = idio_24_gpio_set_multiple;
|
|
|
|
girq = &idio24gpio->chip.irq;
|
|
girq->chip = &idio_24_irqchip;
|
|
/* This will let us handle the parent IRQ in the driver */
|
|
girq->parent_handler = NULL;
|
|
girq->num_parents = 0;
|
|
girq->parents = NULL;
|
|
girq->default_type = IRQ_TYPE_NONE;
|
|
girq->handler = handle_edge_irq;
|
|
|
|
raw_spin_lock_init(&idio24gpio->lock);
|
|
|
|
/* Software board reset */
|
|
iowrite8(0, &idio24gpio->reg->soft_reset);
|
|
/*
|
|
* enable PLX PEX8311 internal PCI wire interrupt and local interrupt
|
|
* input
|
|
*/
|
|
iowrite8((INTCSR_INTERNAL_PCI_WIRE | INTCSR_LOCAL_INPUT) >> 8,
|
|
idio24gpio->plx + PLX_PEX8311_PCI_LCS_INTCSR + 1);
|
|
|
|
err = devm_gpiochip_add_data(dev, &idio24gpio->chip, idio24gpio);
|
|
if (err) {
|
|
dev_err(dev, "GPIO registering failed (%d)\n", err);
|
|
return err;
|
|
}
|
|
|
|
err = devm_request_irq(dev, pdev->irq, idio_24_irq_handler, IRQF_SHARED,
|
|
name, idio24gpio);
|
|
if (err) {
|
|
dev_err(dev, "IRQ handler registering failed (%d)\n", err);
|
|
return err;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct pci_device_id idio_24_pci_dev_id[] = {
|
|
{ PCI_DEVICE(0x494F, 0x0FD0) }, { PCI_DEVICE(0x494F, 0x0BD0) },
|
|
{ PCI_DEVICE(0x494F, 0x07D0) }, { PCI_DEVICE(0x494F, 0x0FC0) },
|
|
{ 0 }
|
|
};
|
|
MODULE_DEVICE_TABLE(pci, idio_24_pci_dev_id);
|
|
|
|
static struct pci_driver idio_24_driver = {
|
|
.name = "pcie-idio-24",
|
|
.id_table = idio_24_pci_dev_id,
|
|
.probe = idio_24_probe
|
|
};
|
|
|
|
module_pci_driver(idio_24_driver);
|
|
|
|
MODULE_AUTHOR("William Breathitt Gray <vilhelm.gray@gmail.com>");
|
|
MODULE_DESCRIPTION("ACCES PCIe-IDIO-24 GPIO driver");
|
|
MODULE_LICENSE("GPL v2");
|