755 lines
22 KiB
C
755 lines
22 KiB
C
/*
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* Copyright 2019 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "amdgpu.h"
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#include "amdgpu_amdkfd.h"
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#include "gc/gc_10_1_0_offset.h"
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#include "gc/gc_10_1_0_sh_mask.h"
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#include "athub/athub_2_0_0_offset.h"
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#include "athub/athub_2_0_0_sh_mask.h"
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#include "oss/osssys_5_0_0_offset.h"
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#include "oss/osssys_5_0_0_sh_mask.h"
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#include "soc15_common.h"
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#include "v10_structs.h"
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#include "nv.h"
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#include "nvd.h"
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enum hqd_dequeue_request_type {
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NO_ACTION = 0,
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DRAIN_PIPE,
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RESET_WAVES,
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SAVE_WAVES
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};
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static void lock_srbm(struct amdgpu_device *adev, uint32_t mec, uint32_t pipe,
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uint32_t queue, uint32_t vmid)
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{
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mutex_lock(&adev->srbm_mutex);
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nv_grbm_select(adev, mec, pipe, queue, vmid);
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}
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static void unlock_srbm(struct amdgpu_device *adev)
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{
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nv_grbm_select(adev, 0, 0, 0, 0);
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mutex_unlock(&adev->srbm_mutex);
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}
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static void acquire_queue(struct amdgpu_device *adev, uint32_t pipe_id,
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uint32_t queue_id)
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{
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uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;
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uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);
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lock_srbm(adev, mec, pipe, queue_id, 0);
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}
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static uint64_t get_queue_mask(struct amdgpu_device *adev,
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uint32_t pipe_id, uint32_t queue_id)
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{
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unsigned int bit = pipe_id * adev->gfx.mec.num_queue_per_pipe +
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queue_id;
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return 1ull << bit;
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}
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static void release_queue(struct amdgpu_device *adev)
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{
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unlock_srbm(adev);
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}
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static void kgd_program_sh_mem_settings(struct amdgpu_device *adev, uint32_t vmid,
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uint32_t sh_mem_config,
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uint32_t sh_mem_ape1_base,
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uint32_t sh_mem_ape1_limit,
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uint32_t sh_mem_bases)
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{
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lock_srbm(adev, 0, 0, 0, vmid);
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WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, sh_mem_config);
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WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
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/* APE1 no longer exists on GFX9 */
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unlock_srbm(adev);
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}
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static int kgd_set_pasid_vmid_mapping(struct amdgpu_device *adev, u32 pasid,
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unsigned int vmid)
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{
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/*
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* We have to assume that there is no outstanding mapping.
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* The ATC_VMID_PASID_MAPPING_UPDATE_STATUS bit could be 0 because
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* a mapping is in progress or because a mapping finished
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* and the SW cleared it.
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* So the protocol is to always wait & clear.
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*/
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uint32_t pasid_mapping = (pasid == 0) ? 0 : (uint32_t)pasid |
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ATC_VMID0_PASID_MAPPING__VALID_MASK;
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pr_debug("pasid 0x%x vmid %d, reg value %x\n", pasid, vmid, pasid_mapping);
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pr_debug("ATHUB, reg %x\n", SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) + vmid);
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WREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) + vmid,
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pasid_mapping);
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#if 0
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/* TODO: uncomment this code when the hardware support is ready. */
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while (!(RREG32(SOC15_REG_OFFSET(
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ATHUB, 0,
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mmATC_VMID_PASID_MAPPING_UPDATE_STATUS)) &
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(1U << vmid)))
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cpu_relax();
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pr_debug("ATHUB mapping update finished\n");
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WREG32(SOC15_REG_OFFSET(ATHUB, 0,
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mmATC_VMID_PASID_MAPPING_UPDATE_STATUS),
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1U << vmid);
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#endif
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/* Mapping vmid to pasid also for IH block */
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pr_debug("update mapping for IH block and mmhub");
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WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid,
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pasid_mapping);
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return 0;
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}
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/* TODO - RING0 form of field is obsolete, seems to date back to SI
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* but still works
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*/
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static int kgd_init_interrupts(struct amdgpu_device *adev, uint32_t pipe_id)
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{
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uint32_t mec;
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uint32_t pipe;
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mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;
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pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);
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lock_srbm(adev, mec, pipe, 0, 0);
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WREG32_SOC15(GC, 0, mmCPC_INT_CNTL,
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CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK |
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CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK);
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unlock_srbm(adev);
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return 0;
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}
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static uint32_t get_sdma_rlc_reg_offset(struct amdgpu_device *adev,
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unsigned int engine_id,
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unsigned int queue_id)
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{
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uint32_t sdma_engine_reg_base[2] = {
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SOC15_REG_OFFSET(SDMA0, 0,
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mmSDMA0_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL,
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/* On gfx10, mmSDMA1_xxx registers are defined NOT based
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* on SDMA1 base address (dw 0x1860) but based on SDMA0
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* base address (dw 0x1260). Therefore use mmSDMA0_RLC0_RB_CNTL
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* instead of mmSDMA1_RLC0_RB_CNTL for the base address calc
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* below
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*/
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SOC15_REG_OFFSET(SDMA1, 0,
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mmSDMA1_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL
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};
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uint32_t retval = sdma_engine_reg_base[engine_id]
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+ queue_id * (mmSDMA0_RLC1_RB_CNTL - mmSDMA0_RLC0_RB_CNTL);
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pr_debug("RLC register offset for SDMA%d RLC%d: 0x%x\n", engine_id,
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queue_id, retval);
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return retval;
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}
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#if 0
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static uint32_t get_watch_base_addr(struct amdgpu_device *adev)
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{
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uint32_t retval = SOC15_REG_OFFSET(GC, 0, mmTCP_WATCH0_ADDR_H) -
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mmTCP_WATCH0_ADDR_H;
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pr_debug("kfd: reg watch base address: 0x%x\n", retval);
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return retval;
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}
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#endif
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static inline struct v10_compute_mqd *get_mqd(void *mqd)
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{
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return (struct v10_compute_mqd *)mqd;
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}
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static inline struct v10_sdma_mqd *get_sdma_mqd(void *mqd)
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{
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return (struct v10_sdma_mqd *)mqd;
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}
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static int kgd_hqd_load(struct amdgpu_device *adev, void *mqd,
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uint32_t pipe_id, uint32_t queue_id,
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uint32_t __user *wptr, uint32_t wptr_shift,
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uint32_t wptr_mask, struct mm_struct *mm)
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{
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struct v10_compute_mqd *m;
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uint32_t *mqd_hqd;
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uint32_t reg, hqd_base, data;
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m = get_mqd(mqd);
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pr_debug("Load hqd of pipe %d queue %d\n", pipe_id, queue_id);
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acquire_queue(adev, pipe_id, queue_id);
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/* HQD registers extend from CP_MQD_BASE_ADDR to CP_HQD_EOP_WPTR_MEM. */
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mqd_hqd = &m->cp_mqd_base_addr_lo;
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hqd_base = SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR);
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for (reg = hqd_base;
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reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++)
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WREG32_SOC15_IP(GC, reg, mqd_hqd[reg - hqd_base]);
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/* Activate doorbell logic before triggering WPTR poll. */
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data = REG_SET_FIELD(m->cp_hqd_pq_doorbell_control,
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CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
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WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, data);
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if (wptr) {
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/* Don't read wptr with get_user because the user
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* context may not be accessible (if this function
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* runs in a work queue). Instead trigger a one-shot
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* polling read from memory in the CP. This assumes
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* that wptr is GPU-accessible in the queue's VMID via
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* ATC or SVM. WPTR==RPTR before starting the poll so
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* the CP starts fetching new commands from the right
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* place.
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*
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* Guessing a 64-bit WPTR from a 32-bit RPTR is a bit
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* tricky. Assume that the queue didn't overflow. The
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* number of valid bits in the 32-bit RPTR depends on
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* the queue size. The remaining bits are taken from
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* the saved 64-bit WPTR. If the WPTR wrapped, add the
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* queue size.
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*/
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uint32_t queue_size =
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2 << REG_GET_FIELD(m->cp_hqd_pq_control,
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CP_HQD_PQ_CONTROL, QUEUE_SIZE);
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uint64_t guessed_wptr = m->cp_hqd_pq_rptr & (queue_size - 1);
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if ((m->cp_hqd_pq_wptr_lo & (queue_size - 1)) < guessed_wptr)
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guessed_wptr += queue_size;
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guessed_wptr += m->cp_hqd_pq_wptr_lo & ~(queue_size - 1);
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guessed_wptr += (uint64_t)m->cp_hqd_pq_wptr_hi << 32;
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WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
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lower_32_bits(guessed_wptr));
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WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
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upper_32_bits(guessed_wptr));
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WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
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lower_32_bits((uint64_t)wptr));
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WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
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upper_32_bits((uint64_t)wptr));
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pr_debug("%s setting CP_PQ_WPTR_POLL_CNTL1 to %x\n", __func__,
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(uint32_t)get_queue_mask(adev, pipe_id, queue_id));
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WREG32_SOC15(GC, 0, mmCP_PQ_WPTR_POLL_CNTL1,
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(uint32_t)get_queue_mask(adev, pipe_id, queue_id));
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}
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/* Start the EOP fetcher */
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WREG32_SOC15(GC, 0, mmCP_HQD_EOP_RPTR,
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REG_SET_FIELD(m->cp_hqd_eop_rptr,
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CP_HQD_EOP_RPTR, INIT_FETCHER, 1));
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data = REG_SET_FIELD(m->cp_hqd_active, CP_HQD_ACTIVE, ACTIVE, 1);
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WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, data);
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release_queue(adev);
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return 0;
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}
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static int kgd_hiq_mqd_load(struct amdgpu_device *adev, void *mqd,
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uint32_t pipe_id, uint32_t queue_id,
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uint32_t doorbell_off)
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{
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struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
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struct v10_compute_mqd *m;
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uint32_t mec, pipe;
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int r;
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m = get_mqd(mqd);
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acquire_queue(adev, pipe_id, queue_id);
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mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;
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pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);
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pr_debug("kfd: set HIQ, mec:%d, pipe:%d, queue:%d.\n",
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mec, pipe, queue_id);
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spin_lock(&adev->gfx.kiq.ring_lock);
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r = amdgpu_ring_alloc(kiq_ring, 7);
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if (r) {
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pr_err("Failed to alloc KIQ (%d).\n", r);
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goto out_unlock;
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}
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amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
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amdgpu_ring_write(kiq_ring,
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PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
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PACKET3_MAP_QUEUES_VMID(m->cp_hqd_vmid) | /* VMID */
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PACKET3_MAP_QUEUES_QUEUE(queue_id) |
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PACKET3_MAP_QUEUES_PIPE(pipe) |
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PACKET3_MAP_QUEUES_ME((mec - 1)) |
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PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
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PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */
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PACKET3_MAP_QUEUES_ENGINE_SEL(1) | /* engine_sel: hiq */
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PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
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amdgpu_ring_write(kiq_ring,
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PACKET3_MAP_QUEUES_DOORBELL_OFFSET(doorbell_off));
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amdgpu_ring_write(kiq_ring, m->cp_mqd_base_addr_lo);
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amdgpu_ring_write(kiq_ring, m->cp_mqd_base_addr_hi);
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amdgpu_ring_write(kiq_ring, m->cp_hqd_pq_wptr_poll_addr_lo);
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amdgpu_ring_write(kiq_ring, m->cp_hqd_pq_wptr_poll_addr_hi);
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amdgpu_ring_commit(kiq_ring);
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out_unlock:
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spin_unlock(&adev->gfx.kiq.ring_lock);
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release_queue(adev);
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return r;
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}
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static int kgd_hqd_dump(struct amdgpu_device *adev,
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uint32_t pipe_id, uint32_t queue_id,
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uint32_t (**dump)[2], uint32_t *n_regs)
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{
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uint32_t i = 0, reg;
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#define HQD_N_REGS 56
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#define DUMP_REG(addr) do { \
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if (WARN_ON_ONCE(i >= HQD_N_REGS)) \
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break; \
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(*dump)[i][0] = (addr) << 2; \
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(*dump)[i++][1] = RREG32_SOC15_IP(GC, addr); \
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} while (0)
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*dump = kmalloc(HQD_N_REGS*2*sizeof(uint32_t), GFP_KERNEL);
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if (*dump == NULL)
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return -ENOMEM;
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acquire_queue(adev, pipe_id, queue_id);
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for (reg = SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR);
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reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++)
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DUMP_REG(reg);
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release_queue(adev);
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WARN_ON_ONCE(i != HQD_N_REGS);
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*n_regs = i;
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return 0;
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}
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static int kgd_hqd_sdma_load(struct amdgpu_device *adev, void *mqd,
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uint32_t __user *wptr, struct mm_struct *mm)
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{
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struct v10_sdma_mqd *m;
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uint32_t sdma_rlc_reg_offset;
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unsigned long end_jiffies;
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uint32_t data;
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uint64_t data64;
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uint64_t __user *wptr64 = (uint64_t __user *)wptr;
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m = get_sdma_mqd(mqd);
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sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, m->sdma_engine_id,
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m->sdma_queue_id);
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WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL,
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m->sdmax_rlcx_rb_cntl & (~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK));
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end_jiffies = msecs_to_jiffies(2000) + jiffies;
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while (true) {
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data = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS);
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if (data & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK)
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break;
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if (time_after(jiffies, end_jiffies)) {
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pr_err("SDMA RLC not idle in %s\n", __func__);
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return -ETIME;
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}
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usleep_range(500, 1000);
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}
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WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL_OFFSET,
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m->sdmax_rlcx_doorbell_offset);
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data = REG_SET_FIELD(m->sdmax_rlcx_doorbell, SDMA0_RLC0_DOORBELL,
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ENABLE, 1);
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WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, data);
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WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR,
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m->sdmax_rlcx_rb_rptr);
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WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_HI,
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m->sdmax_rlcx_rb_rptr_hi);
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WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 1);
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if (read_user_wptr(mm, wptr64, data64)) {
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WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR,
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lower_32_bits(data64));
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WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR_HI,
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upper_32_bits(data64));
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} else {
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WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR,
|
|
m->sdmax_rlcx_rb_rptr);
|
|
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR_HI,
|
|
m->sdmax_rlcx_rb_rptr_hi);
|
|
}
|
|
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 0);
|
|
|
|
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE, m->sdmax_rlcx_rb_base);
|
|
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE_HI,
|
|
m->sdmax_rlcx_rb_base_hi);
|
|
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_ADDR_LO,
|
|
m->sdmax_rlcx_rb_rptr_addr_lo);
|
|
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_ADDR_HI,
|
|
m->sdmax_rlcx_rb_rptr_addr_hi);
|
|
|
|
data = REG_SET_FIELD(m->sdmax_rlcx_rb_cntl, SDMA0_RLC0_RB_CNTL,
|
|
RB_ENABLE, 1);
|
|
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, data);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int kgd_hqd_sdma_dump(struct amdgpu_device *adev,
|
|
uint32_t engine_id, uint32_t queue_id,
|
|
uint32_t (**dump)[2], uint32_t *n_regs)
|
|
{
|
|
uint32_t sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev,
|
|
engine_id, queue_id);
|
|
uint32_t i = 0, reg;
|
|
#undef HQD_N_REGS
|
|
#define HQD_N_REGS (19+6+7+10)
|
|
|
|
*dump = kmalloc(HQD_N_REGS*2*sizeof(uint32_t), GFP_KERNEL);
|
|
if (*dump == NULL)
|
|
return -ENOMEM;
|
|
|
|
for (reg = mmSDMA0_RLC0_RB_CNTL; reg <= mmSDMA0_RLC0_DOORBELL; reg++)
|
|
DUMP_REG(sdma_rlc_reg_offset + reg);
|
|
for (reg = mmSDMA0_RLC0_STATUS; reg <= mmSDMA0_RLC0_CSA_ADDR_HI; reg++)
|
|
DUMP_REG(sdma_rlc_reg_offset + reg);
|
|
for (reg = mmSDMA0_RLC0_IB_SUB_REMAIN;
|
|
reg <= mmSDMA0_RLC0_MINOR_PTR_UPDATE; reg++)
|
|
DUMP_REG(sdma_rlc_reg_offset + reg);
|
|
for (reg = mmSDMA0_RLC0_MIDCMD_DATA0;
|
|
reg <= mmSDMA0_RLC0_MIDCMD_CNTL; reg++)
|
|
DUMP_REG(sdma_rlc_reg_offset + reg);
|
|
|
|
WARN_ON_ONCE(i != HQD_N_REGS);
|
|
*n_regs = i;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static bool kgd_hqd_is_occupied(struct amdgpu_device *adev,
|
|
uint64_t queue_address, uint32_t pipe_id,
|
|
uint32_t queue_id)
|
|
{
|
|
uint32_t act;
|
|
bool retval = false;
|
|
uint32_t low, high;
|
|
|
|
acquire_queue(adev, pipe_id, queue_id);
|
|
act = RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE);
|
|
if (act) {
|
|
low = lower_32_bits(queue_address >> 8);
|
|
high = upper_32_bits(queue_address >> 8);
|
|
|
|
if (low == RREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE) &&
|
|
high == RREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI))
|
|
retval = true;
|
|
}
|
|
release_queue(adev);
|
|
return retval;
|
|
}
|
|
|
|
static bool kgd_hqd_sdma_is_occupied(struct amdgpu_device *adev, void *mqd)
|
|
{
|
|
struct v10_sdma_mqd *m;
|
|
uint32_t sdma_rlc_reg_offset;
|
|
uint32_t sdma_rlc_rb_cntl;
|
|
|
|
m = get_sdma_mqd(mqd);
|
|
sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, m->sdma_engine_id,
|
|
m->sdma_queue_id);
|
|
|
|
sdma_rlc_rb_cntl = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);
|
|
|
|
if (sdma_rlc_rb_cntl & SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK)
|
|
return true;
|
|
|
|
return false;
|
|
}
|
|
|
|
static int kgd_hqd_destroy(struct amdgpu_device *adev, void *mqd,
|
|
enum kfd_preempt_type reset_type,
|
|
unsigned int utimeout, uint32_t pipe_id,
|
|
uint32_t queue_id)
|
|
{
|
|
enum hqd_dequeue_request_type type;
|
|
unsigned long end_jiffies;
|
|
uint32_t temp;
|
|
struct v10_compute_mqd *m = get_mqd(mqd);
|
|
|
|
if (amdgpu_in_reset(adev))
|
|
return -EIO;
|
|
|
|
#if 0
|
|
unsigned long flags;
|
|
int retry;
|
|
#endif
|
|
|
|
acquire_queue(adev, pipe_id, queue_id);
|
|
|
|
if (m->cp_hqd_vmid == 0)
|
|
WREG32_FIELD15(GC, 0, RLC_CP_SCHEDULERS, scheduler1, 0);
|
|
|
|
switch (reset_type) {
|
|
case KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN:
|
|
type = DRAIN_PIPE;
|
|
break;
|
|
case KFD_PREEMPT_TYPE_WAVEFRONT_RESET:
|
|
type = RESET_WAVES;
|
|
break;
|
|
case KFD_PREEMPT_TYPE_WAVEFRONT_SAVE:
|
|
type = SAVE_WAVES;
|
|
break;
|
|
default:
|
|
type = DRAIN_PIPE;
|
|
break;
|
|
}
|
|
|
|
#if 0 /* Is this still needed? */
|
|
/* Workaround: If IQ timer is active and the wait time is close to or
|
|
* equal to 0, dequeueing is not safe. Wait until either the wait time
|
|
* is larger or timer is cleared. Also, ensure that IQ_REQ_PEND is
|
|
* cleared before continuing. Also, ensure wait times are set to at
|
|
* least 0x3.
|
|
*/
|
|
local_irq_save(flags);
|
|
preempt_disable();
|
|
retry = 5000; /* wait for 500 usecs at maximum */
|
|
while (true) {
|
|
temp = RREG32(mmCP_HQD_IQ_TIMER);
|
|
if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, PROCESSING_IQ)) {
|
|
pr_debug("HW is processing IQ\n");
|
|
goto loop;
|
|
}
|
|
if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, ACTIVE)) {
|
|
if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, RETRY_TYPE)
|
|
== 3) /* SEM-rearm is safe */
|
|
break;
|
|
/* Wait time 3 is safe for CP, but our MMIO read/write
|
|
* time is close to 1 microsecond, so check for 10 to
|
|
* leave more buffer room
|
|
*/
|
|
if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, WAIT_TIME)
|
|
>= 10)
|
|
break;
|
|
pr_debug("IQ timer is active\n");
|
|
} else
|
|
break;
|
|
loop:
|
|
if (!retry) {
|
|
pr_err("CP HQD IQ timer status time out\n");
|
|
break;
|
|
}
|
|
ndelay(100);
|
|
--retry;
|
|
}
|
|
retry = 1000;
|
|
while (true) {
|
|
temp = RREG32(mmCP_HQD_DEQUEUE_REQUEST);
|
|
if (!(temp & CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_MASK))
|
|
break;
|
|
pr_debug("Dequeue request is pending\n");
|
|
|
|
if (!retry) {
|
|
pr_err("CP HQD dequeue request time out\n");
|
|
break;
|
|
}
|
|
ndelay(100);
|
|
--retry;
|
|
}
|
|
local_irq_restore(flags);
|
|
preempt_enable();
|
|
#endif
|
|
|
|
WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, type);
|
|
|
|
end_jiffies = (utimeout * HZ / 1000) + jiffies;
|
|
while (true) {
|
|
temp = RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE);
|
|
if (!(temp & CP_HQD_ACTIVE__ACTIVE_MASK))
|
|
break;
|
|
if (time_after(jiffies, end_jiffies)) {
|
|
pr_err("cp queue preemption time out.\n");
|
|
release_queue(adev);
|
|
return -ETIME;
|
|
}
|
|
usleep_range(500, 1000);
|
|
}
|
|
|
|
release_queue(adev);
|
|
return 0;
|
|
}
|
|
|
|
static int kgd_hqd_sdma_destroy(struct amdgpu_device *adev, void *mqd,
|
|
unsigned int utimeout)
|
|
{
|
|
struct v10_sdma_mqd *m;
|
|
uint32_t sdma_rlc_reg_offset;
|
|
uint32_t temp;
|
|
unsigned long end_jiffies = (utimeout * HZ / 1000) + jiffies;
|
|
|
|
m = get_sdma_mqd(mqd);
|
|
sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, m->sdma_engine_id,
|
|
m->sdma_queue_id);
|
|
|
|
temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);
|
|
temp = temp & ~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK;
|
|
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, temp);
|
|
|
|
while (true) {
|
|
temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS);
|
|
if (temp & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK)
|
|
break;
|
|
if (time_after(jiffies, end_jiffies)) {
|
|
pr_err("SDMA RLC not idle in %s\n", __func__);
|
|
return -ETIME;
|
|
}
|
|
usleep_range(500, 1000);
|
|
}
|
|
|
|
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, 0);
|
|
WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL,
|
|
RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL) |
|
|
SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK);
|
|
|
|
m->sdmax_rlcx_rb_rptr = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR);
|
|
m->sdmax_rlcx_rb_rptr_hi =
|
|
RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_HI);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static bool get_atc_vmid_pasid_mapping_info(struct amdgpu_device *adev,
|
|
uint8_t vmid, uint16_t *p_pasid)
|
|
{
|
|
uint32_t value;
|
|
|
|
value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING)
|
|
+ vmid);
|
|
*p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK;
|
|
|
|
return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK);
|
|
}
|
|
|
|
static int kgd_wave_control_execute(struct amdgpu_device *adev,
|
|
uint32_t gfx_index_val,
|
|
uint32_t sq_cmd)
|
|
{
|
|
uint32_t data = 0;
|
|
|
|
mutex_lock(&adev->grbm_idx_mutex);
|
|
|
|
WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, gfx_index_val);
|
|
WREG32_SOC15(GC, 0, mmSQ_CMD, sq_cmd);
|
|
|
|
data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
|
|
INSTANCE_BROADCAST_WRITES, 1);
|
|
data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
|
|
SA_BROADCAST_WRITES, 1);
|
|
data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
|
|
SE_BROADCAST_WRITES, 1);
|
|
|
|
WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
|
|
mutex_unlock(&adev->grbm_idx_mutex);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void set_vm_context_page_table_base(struct amdgpu_device *adev,
|
|
uint32_t vmid, uint64_t page_table_base)
|
|
{
|
|
if (!amdgpu_amdkfd_is_kfd_vmid(adev, vmid)) {
|
|
pr_err("trying to set page table base for wrong VMID %u\n",
|
|
vmid);
|
|
return;
|
|
}
|
|
|
|
/* SDMA is on gfxhub as well for Navi1* series */
|
|
adev->gfxhub.funcs->setup_vm_pt_regs(adev, vmid, page_table_base);
|
|
}
|
|
|
|
static void program_trap_handler_settings(struct amdgpu_device *adev,
|
|
uint32_t vmid, uint64_t tba_addr, uint64_t tma_addr)
|
|
{
|
|
lock_srbm(adev, 0, 0, 0, vmid);
|
|
|
|
/*
|
|
* Program TBA registers
|
|
*/
|
|
WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_SHADER_TBA_LO),
|
|
lower_32_bits(tba_addr >> 8));
|
|
WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_SHADER_TBA_HI),
|
|
upper_32_bits(tba_addr >> 8) |
|
|
(1 << SQ_SHADER_TBA_HI__TRAP_EN__SHIFT));
|
|
|
|
/*
|
|
* Program TMA registers
|
|
*/
|
|
WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_SHADER_TMA_LO),
|
|
lower_32_bits(tma_addr >> 8));
|
|
WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_SHADER_TMA_HI),
|
|
upper_32_bits(tma_addr >> 8));
|
|
|
|
unlock_srbm(adev);
|
|
}
|
|
|
|
const struct kfd2kgd_calls gfx_v10_kfd2kgd = {
|
|
.program_sh_mem_settings = kgd_program_sh_mem_settings,
|
|
.set_pasid_vmid_mapping = kgd_set_pasid_vmid_mapping,
|
|
.init_interrupts = kgd_init_interrupts,
|
|
.hqd_load = kgd_hqd_load,
|
|
.hiq_mqd_load = kgd_hiq_mqd_load,
|
|
.hqd_sdma_load = kgd_hqd_sdma_load,
|
|
.hqd_dump = kgd_hqd_dump,
|
|
.hqd_sdma_dump = kgd_hqd_sdma_dump,
|
|
.hqd_is_occupied = kgd_hqd_is_occupied,
|
|
.hqd_sdma_is_occupied = kgd_hqd_sdma_is_occupied,
|
|
.hqd_destroy = kgd_hqd_destroy,
|
|
.hqd_sdma_destroy = kgd_hqd_sdma_destroy,
|
|
.wave_control_execute = kgd_wave_control_execute,
|
|
.get_atc_vmid_pasid_mapping_info =
|
|
get_atc_vmid_pasid_mapping_info,
|
|
.set_vm_context_page_table_base = set_vm_context_page_table_base,
|
|
.program_trap_handler_settings = program_trap_handler_settings,
|
|
};
|