836 lines
24 KiB
C
836 lines
24 KiB
C
/*
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* Copyright 2018 Advanced Micro Devices, Inc.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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*/
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#include <linux/io-64-nonatomic-lo-hi.h>
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#ifdef CONFIG_X86
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#include <asm/hypervisor.h>
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#endif
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#include "amdgpu.h"
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#include "amdgpu_gmc.h"
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#include "amdgpu_ras.h"
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#include "amdgpu_xgmi.h"
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#include <drm/drm_drv.h>
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#include <drm/ttm/ttm_tt.h>
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/**
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* amdgpu_gmc_pdb0_alloc - allocate vram for pdb0
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*
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* @adev: amdgpu_device pointer
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*
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* Allocate video memory for pdb0 and map it for CPU access
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* Returns 0 for success, error for failure.
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*/
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int amdgpu_gmc_pdb0_alloc(struct amdgpu_device *adev)
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{
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int r;
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struct amdgpu_bo_param bp;
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u64 vram_size = adev->gmc.xgmi.node_segment_size * adev->gmc.xgmi.num_physical_nodes;
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uint32_t pde0_page_shift = adev->gmc.vmid0_page_table_block_size + 21;
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uint32_t npdes = (vram_size + (1ULL << pde0_page_shift) -1) >> pde0_page_shift;
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memset(&bp, 0, sizeof(bp));
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bp.size = PAGE_ALIGN((npdes + 1) * 8);
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bp.byte_align = PAGE_SIZE;
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bp.domain = AMDGPU_GEM_DOMAIN_VRAM;
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bp.flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
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AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
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bp.type = ttm_bo_type_kernel;
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bp.resv = NULL;
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bp.bo_ptr_size = sizeof(struct amdgpu_bo);
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r = amdgpu_bo_create(adev, &bp, &adev->gmc.pdb0_bo);
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if (r)
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return r;
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r = amdgpu_bo_reserve(adev->gmc.pdb0_bo, false);
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if (unlikely(r != 0))
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goto bo_reserve_failure;
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r = amdgpu_bo_pin(adev->gmc.pdb0_bo, AMDGPU_GEM_DOMAIN_VRAM);
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if (r)
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goto bo_pin_failure;
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r = amdgpu_bo_kmap(adev->gmc.pdb0_bo, &adev->gmc.ptr_pdb0);
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if (r)
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goto bo_kmap_failure;
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amdgpu_bo_unreserve(adev->gmc.pdb0_bo);
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return 0;
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bo_kmap_failure:
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amdgpu_bo_unpin(adev->gmc.pdb0_bo);
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bo_pin_failure:
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amdgpu_bo_unreserve(adev->gmc.pdb0_bo);
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bo_reserve_failure:
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amdgpu_bo_unref(&adev->gmc.pdb0_bo);
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return r;
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}
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/**
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* amdgpu_gmc_get_pde_for_bo - get the PDE for a BO
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*
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* @bo: the BO to get the PDE for
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* @level: the level in the PD hirarchy
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* @addr: resulting addr
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* @flags: resulting flags
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*
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* Get the address and flags to be used for a PDE (Page Directory Entry).
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*/
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void amdgpu_gmc_get_pde_for_bo(struct amdgpu_bo *bo, int level,
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uint64_t *addr, uint64_t *flags)
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{
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struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
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switch (bo->tbo.resource->mem_type) {
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case TTM_PL_TT:
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*addr = bo->tbo.ttm->dma_address[0];
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break;
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case TTM_PL_VRAM:
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*addr = amdgpu_bo_gpu_offset(bo);
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break;
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default:
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*addr = 0;
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break;
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}
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*flags = amdgpu_ttm_tt_pde_flags(bo->tbo.ttm, bo->tbo.resource);
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amdgpu_gmc_get_vm_pde(adev, level, addr, flags);
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}
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/*
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* amdgpu_gmc_pd_addr - return the address of the root directory
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*/
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uint64_t amdgpu_gmc_pd_addr(struct amdgpu_bo *bo)
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{
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struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
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uint64_t pd_addr;
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/* TODO: move that into ASIC specific code */
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if (adev->asic_type >= CHIP_VEGA10) {
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uint64_t flags = AMDGPU_PTE_VALID;
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amdgpu_gmc_get_pde_for_bo(bo, -1, &pd_addr, &flags);
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pd_addr |= flags;
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} else {
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pd_addr = amdgpu_bo_gpu_offset(bo);
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}
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return pd_addr;
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}
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/**
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* amdgpu_gmc_set_pte_pde - update the page tables using CPU
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*
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* @adev: amdgpu_device pointer
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* @cpu_pt_addr: cpu address of the page table
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* @gpu_page_idx: entry in the page table to update
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* @addr: dst addr to write into pte/pde
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* @flags: access flags
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*
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* Update the page tables using CPU.
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*/
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int amdgpu_gmc_set_pte_pde(struct amdgpu_device *adev, void *cpu_pt_addr,
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uint32_t gpu_page_idx, uint64_t addr,
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uint64_t flags)
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{
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void __iomem *ptr = (void *)cpu_pt_addr;
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uint64_t value;
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/*
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* The following is for PTE only. GART does not have PDEs.
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*/
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value = addr & 0x0000FFFFFFFFF000ULL;
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value |= flags;
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writeq(value, ptr + (gpu_page_idx * 8));
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return 0;
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}
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/**
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* amdgpu_gmc_agp_addr - return the address in the AGP address space
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*
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* @bo: TTM BO which needs the address, must be in GTT domain
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*
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* Tries to figure out how to access the BO through the AGP aperture. Returns
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* AMDGPU_BO_INVALID_OFFSET if that is not possible.
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*/
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uint64_t amdgpu_gmc_agp_addr(struct ttm_buffer_object *bo)
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{
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struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
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if (bo->ttm->num_pages != 1 || bo->ttm->caching == ttm_cached)
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return AMDGPU_BO_INVALID_OFFSET;
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if (bo->ttm->dma_address[0] + PAGE_SIZE >= adev->gmc.agp_size)
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return AMDGPU_BO_INVALID_OFFSET;
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return adev->gmc.agp_start + bo->ttm->dma_address[0];
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}
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/**
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* amdgpu_gmc_vram_location - try to find VRAM location
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*
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* @adev: amdgpu device structure holding all necessary information
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* @mc: memory controller structure holding memory information
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* @base: base address at which to put VRAM
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*
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* Function will try to place VRAM at base address provided
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* as parameter.
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*/
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void amdgpu_gmc_vram_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc,
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u64 base)
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{
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uint64_t vis_limit = (uint64_t)amdgpu_vis_vram_limit << 20;
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uint64_t limit = (uint64_t)amdgpu_vram_limit << 20;
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mc->vram_start = base;
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mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
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if (limit < mc->real_vram_size)
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mc->real_vram_size = limit;
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if (vis_limit && vis_limit < mc->visible_vram_size)
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mc->visible_vram_size = vis_limit;
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if (mc->real_vram_size < mc->visible_vram_size)
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mc->visible_vram_size = mc->real_vram_size;
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if (mc->xgmi.num_physical_nodes == 0) {
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mc->fb_start = mc->vram_start;
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mc->fb_end = mc->vram_end;
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}
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dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
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mc->mc_vram_size >> 20, mc->vram_start,
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mc->vram_end, mc->real_vram_size >> 20);
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}
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/** amdgpu_gmc_sysvm_location - place vram and gart in sysvm aperture
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*
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* @adev: amdgpu device structure holding all necessary information
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* @mc: memory controller structure holding memory information
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*
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* This function is only used if use GART for FB translation. In such
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* case, we use sysvm aperture (vmid0 page tables) for both vram
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* and gart (aka system memory) access.
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*
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* GPUVM (and our organization of vmid0 page tables) require sysvm
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* aperture to be placed at a location aligned with 8 times of native
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* page size. For example, if vm_context0_cntl.page_table_block_size
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* is 12, then native page size is 8G (2M*2^12), sysvm should start
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* with a 64G aligned address. For simplicity, we just put sysvm at
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* address 0. So vram start at address 0 and gart is right after vram.
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*/
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void amdgpu_gmc_sysvm_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc)
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{
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u64 hive_vram_start = 0;
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u64 hive_vram_end = mc->xgmi.node_segment_size * mc->xgmi.num_physical_nodes - 1;
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mc->vram_start = mc->xgmi.node_segment_size * mc->xgmi.physical_node_id;
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mc->vram_end = mc->vram_start + mc->xgmi.node_segment_size - 1;
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mc->gart_start = hive_vram_end + 1;
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mc->gart_end = mc->gart_start + mc->gart_size - 1;
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mc->fb_start = hive_vram_start;
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mc->fb_end = hive_vram_end;
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dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
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mc->mc_vram_size >> 20, mc->vram_start,
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mc->vram_end, mc->real_vram_size >> 20);
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dev_info(adev->dev, "GART: %lluM 0x%016llX - 0x%016llX\n",
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mc->gart_size >> 20, mc->gart_start, mc->gart_end);
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}
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/**
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* amdgpu_gmc_gart_location - try to find GART location
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*
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* @adev: amdgpu device structure holding all necessary information
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* @mc: memory controller structure holding memory information
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*
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* Function will place try to place GART before or after VRAM.
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* If GART size is bigger than space left then we ajust GART size.
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* Thus function will never fails.
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*/
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void amdgpu_gmc_gart_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc)
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{
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const uint64_t four_gb = 0x100000000ULL;
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u64 size_af, size_bf;
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/*To avoid the hole, limit the max mc address to AMDGPU_GMC_HOLE_START*/
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u64 max_mc_address = min(adev->gmc.mc_mask, AMDGPU_GMC_HOLE_START - 1);
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/* VCE doesn't like it when BOs cross a 4GB segment, so align
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* the GART base on a 4GB boundary as well.
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*/
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size_bf = mc->fb_start;
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size_af = max_mc_address + 1 - ALIGN(mc->fb_end + 1, four_gb);
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if (mc->gart_size > max(size_bf, size_af)) {
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dev_warn(adev->dev, "limiting GART\n");
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mc->gart_size = max(size_bf, size_af);
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}
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if ((size_bf >= mc->gart_size && size_bf < size_af) ||
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(size_af < mc->gart_size))
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mc->gart_start = 0;
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else
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mc->gart_start = max_mc_address - mc->gart_size + 1;
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mc->gart_start &= ~(four_gb - 1);
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mc->gart_end = mc->gart_start + mc->gart_size - 1;
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dev_info(adev->dev, "GART: %lluM 0x%016llX - 0x%016llX\n",
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mc->gart_size >> 20, mc->gart_start, mc->gart_end);
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}
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/**
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* amdgpu_gmc_agp_location - try to find AGP location
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* @adev: amdgpu device structure holding all necessary information
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* @mc: memory controller structure holding memory information
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*
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* Function will place try to find a place for the AGP BAR in the MC address
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* space.
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*
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* AGP BAR will be assigned the largest available hole in the address space.
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* Should be called after VRAM and GART locations are setup.
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*/
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void amdgpu_gmc_agp_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc)
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{
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const uint64_t sixteen_gb = 1ULL << 34;
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const uint64_t sixteen_gb_mask = ~(sixteen_gb - 1);
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u64 size_af, size_bf;
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if (amdgpu_sriov_vf(adev)) {
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mc->agp_start = 0xffffffffffff;
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mc->agp_end = 0x0;
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mc->agp_size = 0;
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return;
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}
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if (mc->fb_start > mc->gart_start) {
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size_bf = (mc->fb_start & sixteen_gb_mask) -
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ALIGN(mc->gart_end + 1, sixteen_gb);
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size_af = mc->mc_mask + 1 - ALIGN(mc->fb_end + 1, sixteen_gb);
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} else {
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size_bf = mc->fb_start & sixteen_gb_mask;
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size_af = (mc->gart_start & sixteen_gb_mask) -
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ALIGN(mc->fb_end + 1, sixteen_gb);
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}
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if (size_bf > size_af) {
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mc->agp_start = (mc->fb_start - size_bf) & sixteen_gb_mask;
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mc->agp_size = size_bf;
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} else {
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mc->agp_start = ALIGN(mc->fb_end + 1, sixteen_gb);
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mc->agp_size = size_af;
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}
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mc->agp_end = mc->agp_start + mc->agp_size - 1;
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dev_info(adev->dev, "AGP: %lluM 0x%016llX - 0x%016llX\n",
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mc->agp_size >> 20, mc->agp_start, mc->agp_end);
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}
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/**
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* amdgpu_gmc_fault_key - get hask key from vm fault address and pasid
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*
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* @addr: 48 bit physical address, page aligned (36 significant bits)
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* @pasid: 16 bit process address space identifier
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*/
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static inline uint64_t amdgpu_gmc_fault_key(uint64_t addr, uint16_t pasid)
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{
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return addr << 4 | pasid;
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}
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/**
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* amdgpu_gmc_filter_faults - filter VM faults
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*
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* @adev: amdgpu device structure
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* @ih: interrupt ring that the fault received from
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* @addr: address of the VM fault
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* @pasid: PASID of the process causing the fault
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* @timestamp: timestamp of the fault
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*
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* Returns:
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* True if the fault was filtered and should not be processed further.
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* False if the fault is a new one and needs to be handled.
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*/
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bool amdgpu_gmc_filter_faults(struct amdgpu_device *adev,
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struct amdgpu_ih_ring *ih, uint64_t addr,
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uint16_t pasid, uint64_t timestamp)
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{
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struct amdgpu_gmc *gmc = &adev->gmc;
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uint64_t stamp, key = amdgpu_gmc_fault_key(addr, pasid);
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struct amdgpu_gmc_fault *fault;
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uint32_t hash;
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/* Stale retry fault if timestamp goes backward */
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if (amdgpu_ih_ts_after(timestamp, ih->processed_timestamp))
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return true;
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/* If we don't have space left in the ring buffer return immediately */
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stamp = max(timestamp, AMDGPU_GMC_FAULT_TIMEOUT + 1) -
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AMDGPU_GMC_FAULT_TIMEOUT;
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if (gmc->fault_ring[gmc->last_fault].timestamp >= stamp)
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return true;
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/* Try to find the fault in the hash */
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hash = hash_64(key, AMDGPU_GMC_FAULT_HASH_ORDER);
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fault = &gmc->fault_ring[gmc->fault_hash[hash].idx];
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while (fault->timestamp >= stamp) {
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uint64_t tmp;
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if (atomic64_read(&fault->key) == key)
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return true;
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tmp = fault->timestamp;
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fault = &gmc->fault_ring[fault->next];
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/* Check if the entry was reused */
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if (fault->timestamp >= tmp)
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break;
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}
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/* Add the fault to the ring */
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fault = &gmc->fault_ring[gmc->last_fault];
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atomic64_set(&fault->key, key);
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fault->timestamp = timestamp;
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/* And update the hash */
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fault->next = gmc->fault_hash[hash].idx;
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gmc->fault_hash[hash].idx = gmc->last_fault++;
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return false;
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}
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/**
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* amdgpu_gmc_filter_faults_remove - remove address from VM faults filter
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*
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* @adev: amdgpu device structure
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* @addr: address of the VM fault
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* @pasid: PASID of the process causing the fault
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*
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* Remove the address from fault filter, then future vm fault on this address
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* will pass to retry fault handler to recover.
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*/
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void amdgpu_gmc_filter_faults_remove(struct amdgpu_device *adev, uint64_t addr,
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uint16_t pasid)
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{
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struct amdgpu_gmc *gmc = &adev->gmc;
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uint64_t key = amdgpu_gmc_fault_key(addr, pasid);
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struct amdgpu_gmc_fault *fault;
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uint32_t hash;
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uint64_t tmp;
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hash = hash_64(key, AMDGPU_GMC_FAULT_HASH_ORDER);
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fault = &gmc->fault_ring[gmc->fault_hash[hash].idx];
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do {
|
|
if (atomic64_cmpxchg(&fault->key, key, 0) == key)
|
|
break;
|
|
|
|
tmp = fault->timestamp;
|
|
fault = &gmc->fault_ring[fault->next];
|
|
} while (fault->timestamp < tmp);
|
|
}
|
|
|
|
int amdgpu_gmc_ras_early_init(struct amdgpu_device *adev)
|
|
{
|
|
if (!adev->gmc.xgmi.connected_to_cpu) {
|
|
adev->gmc.xgmi.ras = &xgmi_ras;
|
|
amdgpu_ras_register_ras_block(adev, &adev->gmc.xgmi.ras->ras_block);
|
|
adev->gmc.xgmi.ras_if = &adev->gmc.xgmi.ras->ras_block.ras_comm;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
int amdgpu_gmc_ras_late_init(struct amdgpu_device *adev)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
void amdgpu_gmc_ras_fini(struct amdgpu_device *adev)
|
|
{
|
|
|
|
}
|
|
|
|
/*
|
|
* The latest engine allocation on gfx9/10 is:
|
|
* Engine 2, 3: firmware
|
|
* Engine 0, 1, 4~16: amdgpu ring,
|
|
* subject to change when ring number changes
|
|
* Engine 17: Gart flushes
|
|
*/
|
|
#define GFXHUB_FREE_VM_INV_ENGS_BITMAP 0x1FFF3
|
|
#define MMHUB_FREE_VM_INV_ENGS_BITMAP 0x1FFF3
|
|
|
|
int amdgpu_gmc_allocate_vm_inv_eng(struct amdgpu_device *adev)
|
|
{
|
|
struct amdgpu_ring *ring;
|
|
unsigned vm_inv_engs[AMDGPU_MAX_VMHUBS] =
|
|
{GFXHUB_FREE_VM_INV_ENGS_BITMAP, MMHUB_FREE_VM_INV_ENGS_BITMAP,
|
|
GFXHUB_FREE_VM_INV_ENGS_BITMAP};
|
|
unsigned i;
|
|
unsigned vmhub, inv_eng;
|
|
|
|
if (adev->enable_mes) {
|
|
/* reserve engine 5 for firmware */
|
|
for (vmhub = 0; vmhub < AMDGPU_MAX_VMHUBS; vmhub++)
|
|
vm_inv_engs[vmhub] &= ~(1 << 5);
|
|
}
|
|
|
|
for (i = 0; i < adev->num_rings; ++i) {
|
|
ring = adev->rings[i];
|
|
vmhub = ring->funcs->vmhub;
|
|
|
|
if (ring == &adev->mes.ring)
|
|
continue;
|
|
|
|
inv_eng = ffs(vm_inv_engs[vmhub]);
|
|
if (!inv_eng) {
|
|
dev_err(adev->dev, "no VM inv eng for ring %s\n",
|
|
ring->name);
|
|
return -EINVAL;
|
|
}
|
|
|
|
ring->vm_inv_eng = inv_eng - 1;
|
|
vm_inv_engs[vmhub] &= ~(1 << ring->vm_inv_eng);
|
|
|
|
dev_info(adev->dev, "ring %s uses VM inv eng %u on hub %u\n",
|
|
ring->name, ring->vm_inv_eng, ring->funcs->vmhub);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* amdgpu_gmc_tmz_set -- check and set if a device supports TMZ
|
|
* @adev: amdgpu_device pointer
|
|
*
|
|
* Check and set if an the device @adev supports Trusted Memory
|
|
* Zones (TMZ).
|
|
*/
|
|
void amdgpu_gmc_tmz_set(struct amdgpu_device *adev)
|
|
{
|
|
switch (adev->ip_versions[GC_HWIP][0]) {
|
|
/* RAVEN */
|
|
case IP_VERSION(9, 2, 2):
|
|
case IP_VERSION(9, 1, 0):
|
|
/* RENOIR looks like RAVEN */
|
|
case IP_VERSION(9, 3, 0):
|
|
/* GC 10.3.7 */
|
|
case IP_VERSION(10, 3, 7):
|
|
/* GC 11.0.1 */
|
|
case IP_VERSION(11, 0, 1):
|
|
if (amdgpu_tmz == 0) {
|
|
adev->gmc.tmz_enabled = false;
|
|
dev_info(adev->dev,
|
|
"Trusted Memory Zone (TMZ) feature disabled (cmd line)\n");
|
|
} else {
|
|
adev->gmc.tmz_enabled = true;
|
|
dev_info(adev->dev,
|
|
"Trusted Memory Zone (TMZ) feature enabled\n");
|
|
}
|
|
break;
|
|
case IP_VERSION(10, 1, 10):
|
|
case IP_VERSION(10, 1, 1):
|
|
case IP_VERSION(10, 1, 2):
|
|
case IP_VERSION(10, 1, 3):
|
|
case IP_VERSION(10, 3, 0):
|
|
case IP_VERSION(10, 3, 2):
|
|
case IP_VERSION(10, 3, 4):
|
|
case IP_VERSION(10, 3, 5):
|
|
case IP_VERSION(10, 3, 6):
|
|
/* VANGOGH */
|
|
case IP_VERSION(10, 3, 1):
|
|
/* YELLOW_CARP*/
|
|
case IP_VERSION(10, 3, 3):
|
|
case IP_VERSION(11, 0, 4):
|
|
/* Don't enable it by default yet.
|
|
*/
|
|
if (amdgpu_tmz < 1) {
|
|
adev->gmc.tmz_enabled = false;
|
|
dev_info(adev->dev,
|
|
"Trusted Memory Zone (TMZ) feature disabled as experimental (default)\n");
|
|
} else {
|
|
adev->gmc.tmz_enabled = true;
|
|
dev_info(adev->dev,
|
|
"Trusted Memory Zone (TMZ) feature enabled as experimental (cmd line)\n");
|
|
}
|
|
break;
|
|
default:
|
|
adev->gmc.tmz_enabled = false;
|
|
dev_info(adev->dev,
|
|
"Trusted Memory Zone (TMZ) feature not supported\n");
|
|
break;
|
|
}
|
|
}
|
|
|
|
/**
|
|
* amdgpu_gmc_noretry_set -- set per asic noretry defaults
|
|
* @adev: amdgpu_device pointer
|
|
*
|
|
* Set a per asic default for the no-retry parameter.
|
|
*
|
|
*/
|
|
void amdgpu_gmc_noretry_set(struct amdgpu_device *adev)
|
|
{
|
|
struct amdgpu_gmc *gmc = &adev->gmc;
|
|
uint32_t gc_ver = adev->ip_versions[GC_HWIP][0];
|
|
bool noretry_default = (gc_ver == IP_VERSION(9, 0, 1) ||
|
|
gc_ver == IP_VERSION(9, 3, 0) ||
|
|
gc_ver == IP_VERSION(9, 4, 0) ||
|
|
gc_ver == IP_VERSION(9, 4, 1) ||
|
|
gc_ver == IP_VERSION(9, 4, 2) ||
|
|
gc_ver >= IP_VERSION(10, 3, 0));
|
|
|
|
gmc->noretry = (amdgpu_noretry == -1) ? noretry_default : amdgpu_noretry;
|
|
}
|
|
|
|
void amdgpu_gmc_set_vm_fault_masks(struct amdgpu_device *adev, int hub_type,
|
|
bool enable)
|
|
{
|
|
struct amdgpu_vmhub *hub;
|
|
u32 tmp, reg, i;
|
|
|
|
hub = &adev->vmhub[hub_type];
|
|
for (i = 0; i < 16; i++) {
|
|
reg = hub->vm_context0_cntl + hub->ctx_distance * i;
|
|
|
|
tmp = (hub_type == AMDGPU_GFXHUB_0) ?
|
|
RREG32_SOC15_IP(GC, reg) :
|
|
RREG32_SOC15_IP(MMHUB, reg);
|
|
|
|
if (enable)
|
|
tmp |= hub->vm_cntx_cntl_vm_fault;
|
|
else
|
|
tmp &= ~hub->vm_cntx_cntl_vm_fault;
|
|
|
|
(hub_type == AMDGPU_GFXHUB_0) ?
|
|
WREG32_SOC15_IP(GC, reg, tmp) :
|
|
WREG32_SOC15_IP(MMHUB, reg, tmp);
|
|
}
|
|
}
|
|
|
|
void amdgpu_gmc_get_vbios_allocations(struct amdgpu_device *adev)
|
|
{
|
|
unsigned size;
|
|
|
|
/*
|
|
* Some ASICs need to reserve a region of video memory to avoid access
|
|
* from driver
|
|
*/
|
|
adev->mman.stolen_reserved_offset = 0;
|
|
adev->mman.stolen_reserved_size = 0;
|
|
|
|
/*
|
|
* TODO:
|
|
* Currently there is a bug where some memory client outside
|
|
* of the driver writes to first 8M of VRAM on S3 resume,
|
|
* this overrides GART which by default gets placed in first 8M and
|
|
* causes VM_FAULTS once GTT is accessed.
|
|
* Keep the stolen memory reservation until the while this is not solved.
|
|
*/
|
|
switch (adev->asic_type) {
|
|
case CHIP_VEGA10:
|
|
adev->mman.keep_stolen_vga_memory = true;
|
|
/*
|
|
* VEGA10 SRIOV VF with MS_HYPERV host needs some firmware reserved area.
|
|
*/
|
|
#ifdef CONFIG_X86
|
|
if (amdgpu_sriov_vf(adev) && hypervisor_is_type(X86_HYPER_MS_HYPERV)) {
|
|
adev->mman.stolen_reserved_offset = 0x500000;
|
|
adev->mman.stolen_reserved_size = 0x200000;
|
|
}
|
|
#endif
|
|
break;
|
|
case CHIP_RAVEN:
|
|
case CHIP_RENOIR:
|
|
adev->mman.keep_stolen_vga_memory = true;
|
|
break;
|
|
case CHIP_YELLOW_CARP:
|
|
if (amdgpu_discovery == 0) {
|
|
adev->mman.stolen_reserved_offset = 0x1ffb0000;
|
|
adev->mman.stolen_reserved_size = 64 * PAGE_SIZE;
|
|
}
|
|
break;
|
|
default:
|
|
adev->mman.keep_stolen_vga_memory = false;
|
|
break;
|
|
}
|
|
|
|
if (amdgpu_sriov_vf(adev) ||
|
|
!amdgpu_device_has_display_hardware(adev)) {
|
|
size = 0;
|
|
} else {
|
|
size = amdgpu_gmc_get_vbios_fb_size(adev);
|
|
|
|
if (adev->mman.keep_stolen_vga_memory)
|
|
size = max(size, (unsigned)AMDGPU_VBIOS_VGA_ALLOCATION);
|
|
}
|
|
|
|
/* set to 0 if the pre-OS buffer uses up most of vram */
|
|
if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024))
|
|
size = 0;
|
|
|
|
if (size > AMDGPU_VBIOS_VGA_ALLOCATION) {
|
|
adev->mman.stolen_vga_size = AMDGPU_VBIOS_VGA_ALLOCATION;
|
|
adev->mman.stolen_extended_size = size - adev->mman.stolen_vga_size;
|
|
} else {
|
|
adev->mman.stolen_vga_size = size;
|
|
adev->mman.stolen_extended_size = 0;
|
|
}
|
|
}
|
|
|
|
/**
|
|
* amdgpu_gmc_init_pdb0 - initialize PDB0
|
|
*
|
|
* @adev: amdgpu_device pointer
|
|
*
|
|
* This function is only used when GART page table is used
|
|
* for FB address translatioin. In such a case, we construct
|
|
* a 2-level system VM page table: PDB0->PTB, to cover both
|
|
* VRAM of the hive and system memory.
|
|
*
|
|
* PDB0 is static, initialized once on driver initialization.
|
|
* The first n entries of PDB0 are used as PTE by setting
|
|
* P bit to 1, pointing to VRAM. The n+1'th entry points
|
|
* to a big PTB covering system memory.
|
|
*
|
|
*/
|
|
void amdgpu_gmc_init_pdb0(struct amdgpu_device *adev)
|
|
{
|
|
int i;
|
|
uint64_t flags = adev->gart.gart_pte_flags; //TODO it is UC. explore NC/RW?
|
|
/* Each PDE0 (used as PTE) covers (2^vmid0_page_table_block_size)*2M
|
|
*/
|
|
u64 vram_size = adev->gmc.xgmi.node_segment_size * adev->gmc.xgmi.num_physical_nodes;
|
|
u64 pde0_page_size = (1ULL<<adev->gmc.vmid0_page_table_block_size)<<21;
|
|
u64 vram_addr = adev->vm_manager.vram_base_offset -
|
|
adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size;
|
|
u64 vram_end = vram_addr + vram_size;
|
|
u64 gart_ptb_gpu_pa = amdgpu_gmc_vram_pa(adev, adev->gart.bo);
|
|
int idx;
|
|
|
|
if (!drm_dev_enter(adev_to_drm(adev), &idx))
|
|
return;
|
|
|
|
flags |= AMDGPU_PTE_VALID | AMDGPU_PTE_READABLE;
|
|
flags |= AMDGPU_PTE_WRITEABLE;
|
|
flags |= AMDGPU_PTE_SNOOPED;
|
|
flags |= AMDGPU_PTE_FRAG((adev->gmc.vmid0_page_table_block_size + 9*1));
|
|
flags |= AMDGPU_PDE_PTE;
|
|
|
|
/* The first n PDE0 entries are used as PTE,
|
|
* pointing to vram
|
|
*/
|
|
for (i = 0; vram_addr < vram_end; i++, vram_addr += pde0_page_size)
|
|
amdgpu_gmc_set_pte_pde(adev, adev->gmc.ptr_pdb0, i, vram_addr, flags);
|
|
|
|
/* The n+1'th PDE0 entry points to a huge
|
|
* PTB who has more than 512 entries each
|
|
* pointing to a 4K system page
|
|
*/
|
|
flags = AMDGPU_PTE_VALID;
|
|
flags |= AMDGPU_PDE_BFS(0) | AMDGPU_PTE_SNOOPED;
|
|
/* Requires gart_ptb_gpu_pa to be 4K aligned */
|
|
amdgpu_gmc_set_pte_pde(adev, adev->gmc.ptr_pdb0, i, gart_ptb_gpu_pa, flags);
|
|
drm_dev_exit(idx);
|
|
}
|
|
|
|
/**
|
|
* amdgpu_gmc_vram_mc2pa - calculate vram buffer's physical address from MC
|
|
* address
|
|
*
|
|
* @adev: amdgpu_device pointer
|
|
* @mc_addr: MC address of buffer
|
|
*/
|
|
uint64_t amdgpu_gmc_vram_mc2pa(struct amdgpu_device *adev, uint64_t mc_addr)
|
|
{
|
|
return mc_addr - adev->gmc.vram_start + adev->vm_manager.vram_base_offset;
|
|
}
|
|
|
|
/**
|
|
* amdgpu_gmc_vram_pa - calculate vram buffer object's physical address from
|
|
* GPU's view
|
|
*
|
|
* @adev: amdgpu_device pointer
|
|
* @bo: amdgpu buffer object
|
|
*/
|
|
uint64_t amdgpu_gmc_vram_pa(struct amdgpu_device *adev, struct amdgpu_bo *bo)
|
|
{
|
|
return amdgpu_gmc_vram_mc2pa(adev, amdgpu_bo_gpu_offset(bo));
|
|
}
|
|
|
|
/**
|
|
* amdgpu_gmc_vram_cpu_pa - calculate vram buffer object's physical address
|
|
* from CPU's view
|
|
*
|
|
* @adev: amdgpu_device pointer
|
|
* @bo: amdgpu buffer object
|
|
*/
|
|
uint64_t amdgpu_gmc_vram_cpu_pa(struct amdgpu_device *adev, struct amdgpu_bo *bo)
|
|
{
|
|
return amdgpu_bo_gpu_offset(bo) - adev->gmc.vram_start + adev->gmc.aper_base;
|
|
}
|
|
|
|
int amdgpu_gmc_vram_checking(struct amdgpu_device *adev)
|
|
{
|
|
struct amdgpu_bo *vram_bo = NULL;
|
|
uint64_t vram_gpu = 0;
|
|
void *vram_ptr = NULL;
|
|
|
|
int ret, size = 0x100000;
|
|
uint8_t cptr[10];
|
|
|
|
ret = amdgpu_bo_create_kernel(adev, size, PAGE_SIZE,
|
|
AMDGPU_GEM_DOMAIN_VRAM,
|
|
&vram_bo,
|
|
&vram_gpu,
|
|
&vram_ptr);
|
|
if (ret)
|
|
return ret;
|
|
|
|
memset(vram_ptr, 0x86, size);
|
|
memset(cptr, 0x86, 10);
|
|
|
|
/**
|
|
* Check the start, the mid, and the end of the memory if the content of
|
|
* each byte is the pattern "0x86". If yes, we suppose the vram bo is
|
|
* workable.
|
|
*
|
|
* Note: If check the each byte of whole 1M bo, it will cost too many
|
|
* seconds, so here, we just pick up three parts for emulation.
|
|
*/
|
|
ret = memcmp(vram_ptr, cptr, 10);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = memcmp(vram_ptr + (size / 2), cptr, 10);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = memcmp(vram_ptr + size - 10, cptr, 10);
|
|
if (ret)
|
|
return ret;
|
|
|
|
amdgpu_bo_free_kernel(&vram_bo, &vram_gpu,
|
|
&vram_ptr);
|
|
|
|
return 0;
|
|
}
|