504 lines
16 KiB
C
504 lines
16 KiB
C
/*
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* Copyright 2022 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "umc_v8_10.h"
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#include "amdgpu_ras.h"
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#include "amdgpu_umc.h"
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#include "amdgpu.h"
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#include "umc/umc_8_10_0_offset.h"
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#include "umc/umc_8_10_0_sh_mask.h"
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#define UMC_8_NODE_DIST 0x800000
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#define UMC_8_INST_DIST 0x4000
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struct channelnum_map_colbit {
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uint32_t channel_num;
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uint32_t col_bit;
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};
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const struct channelnum_map_colbit umc_v8_10_channelnum_map_colbit_table[] = {
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{24, 13},
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{20, 13},
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{16, 12},
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{14, 12},
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{12, 12},
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{10, 12},
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{6, 11},
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};
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const uint32_t
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umc_v8_10_channel_idx_tbl_ext0[]
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[UMC_V8_10_UMC_INSTANCE_NUM]
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[UMC_V8_10_CHANNEL_INSTANCE_NUM] = {
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{{1, 5}, {7, 3}},
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{{14, 15}, {13, 12}},
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{{10, 11}, {9, 8}},
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{{6, 2}, {0, 4}}
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};
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const uint32_t
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umc_v8_10_channel_idx_tbl[]
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[UMC_V8_10_UMC_INSTANCE_NUM]
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[UMC_V8_10_CHANNEL_INSTANCE_NUM] = {
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{{16, 18}, {17, 19}},
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{{15, 11}, {3, 7}},
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{{1, 5}, {13, 9}},
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{{23, 21}, {22, 20}},
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{{0, 4}, {12, 8}},
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{{14, 10}, {2, 6}}
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};
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static inline uint32_t get_umc_v8_10_reg_offset(struct amdgpu_device *adev,
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uint32_t node_inst,
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uint32_t umc_inst,
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uint32_t ch_inst)
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{
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return adev->umc.channel_offs * ch_inst + UMC_8_INST_DIST * umc_inst +
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UMC_8_NODE_DIST * node_inst;
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}
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static void umc_v8_10_clear_error_count_per_channel(struct amdgpu_device *adev,
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uint32_t umc_reg_offset)
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{
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uint32_t ecc_err_cnt_addr;
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ecc_err_cnt_addr =
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SOC15_REG_OFFSET(UMC, 0, regUMCCH0_0_GeccErrCnt);
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/* clear error count */
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WREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4,
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UMC_V8_10_CE_CNT_INIT);
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}
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static void umc_v8_10_clear_error_count(struct amdgpu_device *adev)
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{
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uint32_t node_inst = 0;
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uint32_t umc_inst = 0;
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uint32_t ch_inst = 0;
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uint32_t umc_reg_offset = 0;
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LOOP_UMC_EACH_NODE_INST_AND_CH(node_inst, umc_inst, ch_inst) {
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umc_reg_offset = get_umc_v8_10_reg_offset(adev,
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node_inst,
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umc_inst,
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ch_inst);
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umc_v8_10_clear_error_count_per_channel(adev,
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umc_reg_offset);
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}
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}
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static void umc_v8_10_query_correctable_error_count(struct amdgpu_device *adev,
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uint32_t umc_reg_offset,
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unsigned long *error_count)
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{
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uint64_t mc_umc_status;
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uint32_t mc_umc_status_addr;
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/* UMC 8_10 registers */
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mc_umc_status_addr =
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SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_STATUST0);
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/* Rely on MCUMC_STATUS for correctable error counter
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* MCUMC_STATUS is a 64 bit register
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*/
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mc_umc_status = RREG64_PCIE((mc_umc_status_addr + umc_reg_offset) * 4);
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if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &&
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REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1)
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*error_count += 1;
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}
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static void umc_v8_10_query_uncorrectable_error_count(struct amdgpu_device *adev,
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uint32_t umc_reg_offset,
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unsigned long *error_count)
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{
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uint64_t mc_umc_status;
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uint32_t mc_umc_status_addr;
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mc_umc_status_addr = SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_STATUST0);
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/* Check the MCUMC_STATUS. */
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mc_umc_status = RREG64_PCIE((mc_umc_status_addr + umc_reg_offset) * 4);
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if ((REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1) &&
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(REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Deferred) == 1 ||
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REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 ||
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REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, PCC) == 1 ||
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REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UC) == 1 ||
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REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, TCC) == 1))
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*error_count += 1;
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}
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static void umc_v8_10_query_ras_error_count(struct amdgpu_device *adev,
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void *ras_error_status)
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{
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struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
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uint32_t node_inst = 0;
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uint32_t umc_inst = 0;
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uint32_t ch_inst = 0;
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uint32_t umc_reg_offset = 0;
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LOOP_UMC_EACH_NODE_INST_AND_CH(node_inst, umc_inst, ch_inst) {
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umc_reg_offset = get_umc_v8_10_reg_offset(adev,
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node_inst,
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umc_inst,
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ch_inst);
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umc_v8_10_query_correctable_error_count(adev,
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umc_reg_offset,
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&(err_data->ce_count));
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umc_v8_10_query_uncorrectable_error_count(adev,
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umc_reg_offset,
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&(err_data->ue_count));
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}
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umc_v8_10_clear_error_count(adev);
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}
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static uint32_t umc_v8_10_get_col_bit(uint32_t channel_num)
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{
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uint32_t t = 0;
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for (t = 0; t < ARRAY_SIZE(umc_v8_10_channelnum_map_colbit_table); t++)
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if (channel_num == umc_v8_10_channelnum_map_colbit_table[t].channel_num)
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return umc_v8_10_channelnum_map_colbit_table[t].col_bit;
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/* Failed to get col_bit. */
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return U32_MAX;
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}
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/*
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* Mapping normal address to soc physical address in swizzle mode.
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*/
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static int umc_v8_10_swizzle_mode_na_to_pa(struct amdgpu_device *adev,
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uint32_t channel_idx,
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uint64_t na, uint64_t *soc_pa)
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{
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uint32_t channel_num = UMC_V8_10_TOTAL_CHANNEL_NUM(adev);
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uint32_t col_bit = umc_v8_10_get_col_bit(channel_num);
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uint64_t tmp_addr;
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if (col_bit == U32_MAX)
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return -1;
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tmp_addr = SWIZZLE_MODE_TMP_ADDR(na, channel_num, channel_idx);
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*soc_pa = SWIZZLE_MODE_ADDR_HI(tmp_addr, col_bit) |
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SWIZZLE_MODE_ADDR_MID(na, col_bit) |
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SWIZZLE_MODE_ADDR_LOW(tmp_addr, col_bit) |
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SWIZZLE_MODE_ADDR_LSB(na);
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return 0;
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}
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static void umc_v8_10_convert_error_address(struct amdgpu_device *adev,
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struct ras_err_data *err_data, uint64_t err_addr,
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uint32_t ch_inst, uint32_t umc_inst,
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uint32_t node_inst, uint64_t mc_umc_status)
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{
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uint64_t na_err_addr_base;
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uint64_t na_err_addr, retired_page_addr;
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uint32_t channel_index, addr_lsb, col = 0;
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int ret = 0;
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channel_index =
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adev->umc.channel_idx_tbl[node_inst * adev->umc.umc_inst_num *
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adev->umc.channel_inst_num +
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umc_inst * adev->umc.channel_inst_num +
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ch_inst];
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/* the lowest lsb bits should be ignored */
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addr_lsb = REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, AddrLsb);
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err_addr &= ~((0x1ULL << addr_lsb) - 1);
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na_err_addr_base = err_addr & ~(0x3ULL << UMC_V8_10_NA_C5_BIT);
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/* loop for all possibilities of [C6 C5] in normal address. */
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for (col = 0; col < UMC_V8_10_NA_COL_2BITS_POWER_OF_2_NUM; col++) {
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na_err_addr = na_err_addr_base | (col << UMC_V8_10_NA_C5_BIT);
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/* Mapping normal error address to retired soc physical address. */
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ret = umc_v8_10_swizzle_mode_na_to_pa(adev, channel_index,
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na_err_addr, &retired_page_addr);
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if (ret) {
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dev_err(adev->dev, "Failed to map pa from umc na.\n");
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break;
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}
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dev_info(adev->dev, "Error Address(PA): 0x%llx\n",
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retired_page_addr);
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amdgpu_umc_fill_error_record(err_data, na_err_addr,
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retired_page_addr, channel_index, umc_inst);
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}
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}
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static void umc_v8_10_query_error_address(struct amdgpu_device *adev,
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struct ras_err_data *err_data,
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uint32_t umc_reg_offset,
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uint32_t node_inst,
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uint32_t ch_inst,
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uint32_t umc_inst)
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{
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uint64_t mc_umc_status_addr;
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uint64_t mc_umc_status, err_addr;
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uint64_t mc_umc_addrt0;
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mc_umc_status_addr =
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SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_STATUST0);
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mc_umc_status = RREG64_PCIE((mc_umc_status_addr + umc_reg_offset) * 4);
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if (mc_umc_status == 0)
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return;
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if (!err_data->err_addr) {
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/* clear umc status */
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WREG64_PCIE((mc_umc_status_addr + umc_reg_offset) * 4, 0x0ULL);
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return;
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}
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/* calculate error address if ue error is detected */
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if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &&
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REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, AddrV) == 1 &&
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REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1) {
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mc_umc_addrt0 = SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_ADDRT0);
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err_addr = RREG64_PCIE((mc_umc_addrt0 + umc_reg_offset) * 4);
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err_addr = REG_GET_FIELD(err_addr, MCA_UMC_UMC0_MCUMC_ADDRT0, ErrorAddr);
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umc_v8_10_convert_error_address(adev, err_data, err_addr,
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ch_inst, umc_inst, node_inst, mc_umc_status);
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}
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/* clear umc status */
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WREG64_PCIE((mc_umc_status_addr + umc_reg_offset) * 4, 0x0ULL);
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}
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static void umc_v8_10_query_ras_error_address(struct amdgpu_device *adev,
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void *ras_error_status)
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{
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struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
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uint32_t node_inst = 0;
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uint32_t umc_inst = 0;
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uint32_t ch_inst = 0;
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uint32_t umc_reg_offset = 0;
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LOOP_UMC_EACH_NODE_INST_AND_CH(node_inst, umc_inst, ch_inst) {
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umc_reg_offset = get_umc_v8_10_reg_offset(adev,
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node_inst,
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umc_inst,
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ch_inst);
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umc_v8_10_query_error_address(adev,
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err_data,
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umc_reg_offset,
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node_inst,
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ch_inst,
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umc_inst);
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}
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}
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static void umc_v8_10_err_cnt_init_per_channel(struct amdgpu_device *adev,
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uint32_t umc_reg_offset)
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{
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uint32_t ecc_err_cnt_sel, ecc_err_cnt_sel_addr;
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uint32_t ecc_err_cnt_addr;
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ecc_err_cnt_sel_addr =
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SOC15_REG_OFFSET(UMC, 0, regUMCCH0_0_GeccErrCntSel);
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ecc_err_cnt_addr =
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SOC15_REG_OFFSET(UMC, 0, regUMCCH0_0_GeccErrCnt);
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ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4);
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/* set ce error interrupt type to APIC based interrupt */
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ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel, UMCCH0_0_GeccErrCntSel,
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GeccErrInt, 0x1);
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WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, ecc_err_cnt_sel);
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/* set error count to initial value */
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WREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4, UMC_V8_10_CE_CNT_INIT);
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}
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static void umc_v8_10_err_cnt_init(struct amdgpu_device *adev)
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{
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uint32_t node_inst = 0;
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uint32_t umc_inst = 0;
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uint32_t ch_inst = 0;
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uint32_t umc_reg_offset = 0;
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LOOP_UMC_EACH_NODE_INST_AND_CH(node_inst, umc_inst, ch_inst) {
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umc_reg_offset = get_umc_v8_10_reg_offset(adev,
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node_inst,
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umc_inst,
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ch_inst);
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umc_v8_10_err_cnt_init_per_channel(adev, umc_reg_offset);
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}
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}
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static bool umc_v8_10_query_ras_poison_mode(struct amdgpu_device *adev)
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{
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/*
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* Force return true, because UMCCH0_0_GeccCtrl
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* is not accessible from host side
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*/
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return true;
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}
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static void umc_v8_10_ecc_info_query_correctable_error_count(struct amdgpu_device *adev,
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uint32_t node_inst, uint32_t umc_inst, uint32_t ch_inst,
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unsigned long *error_count)
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{
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uint64_t mc_umc_status;
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uint32_t eccinfo_table_idx;
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struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
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eccinfo_table_idx = node_inst * adev->umc.umc_inst_num *
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adev->umc.channel_inst_num +
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umc_inst * adev->umc.channel_inst_num +
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ch_inst;
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/* check the MCUMC_STATUS */
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mc_umc_status = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_status;
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if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &&
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REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1) {
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*error_count += 1;
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}
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}
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static void umc_v8_10_ecc_info_query_uncorrectable_error_count(struct amdgpu_device *adev,
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uint32_t node_inst, uint32_t umc_inst, uint32_t ch_inst,
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unsigned long *error_count)
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{
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uint64_t mc_umc_status;
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uint32_t eccinfo_table_idx;
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struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
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eccinfo_table_idx = node_inst * adev->umc.umc_inst_num *
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adev->umc.channel_inst_num +
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umc_inst * adev->umc.channel_inst_num +
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ch_inst;
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/* check the MCUMC_STATUS */
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mc_umc_status = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_status;
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if ((REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1) &&
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(REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Deferred) == 1 ||
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REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 ||
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REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, PCC) == 1 ||
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REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UC) == 1 ||
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REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, TCC) == 1)) {
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*error_count += 1;
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}
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}
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static void umc_v8_10_ecc_info_query_ras_error_count(struct amdgpu_device *adev,
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void *ras_error_status)
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{
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struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
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uint32_t node_inst = 0;
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uint32_t umc_inst = 0;
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uint32_t ch_inst = 0;
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/* TODO: driver needs to toggle DF Cstate to ensure
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* safe access of UMC registers. Will add the protection
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*/
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LOOP_UMC_EACH_NODE_INST_AND_CH(node_inst, umc_inst, ch_inst) {
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umc_v8_10_ecc_info_query_correctable_error_count(adev,
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node_inst, umc_inst, ch_inst,
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&(err_data->ce_count));
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umc_v8_10_ecc_info_query_uncorrectable_error_count(adev,
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node_inst, umc_inst, ch_inst,
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&(err_data->ue_count));
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}
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}
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static void umc_v8_10_ecc_info_query_error_address(struct amdgpu_device *adev,
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struct ras_err_data *err_data,
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uint32_t ch_inst,
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uint32_t umc_inst,
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uint32_t node_inst)
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{
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uint32_t eccinfo_table_idx;
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uint64_t mc_umc_status, err_addr;
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struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
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eccinfo_table_idx = node_inst * adev->umc.umc_inst_num *
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adev->umc.channel_inst_num +
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umc_inst * adev->umc.channel_inst_num +
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ch_inst;
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mc_umc_status = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_status;
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if (mc_umc_status == 0)
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return;
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if (!err_data->err_addr)
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return;
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/* calculate error address if ue error is detected */
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if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &&
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REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, AddrV) == 1 &&
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(REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1)) {
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err_addr = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_addr;
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err_addr = REG_GET_FIELD(err_addr, MCA_UMC_UMC0_MCUMC_ADDRT0, ErrorAddr);
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umc_v8_10_convert_error_address(adev, err_data, err_addr,
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ch_inst, umc_inst, node_inst, mc_umc_status);
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}
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}
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static void umc_v8_10_ecc_info_query_ras_error_address(struct amdgpu_device *adev,
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void *ras_error_status)
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{
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struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
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uint32_t node_inst = 0;
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uint32_t umc_inst = 0;
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uint32_t ch_inst = 0;
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/* TODO: driver needs to toggle DF Cstate to ensure
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* safe access of UMC resgisters. Will add the protection
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* when firmware interface is ready
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*/
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LOOP_UMC_EACH_NODE_INST_AND_CH(node_inst, umc_inst, ch_inst) {
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umc_v8_10_ecc_info_query_error_address(adev,
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err_data,
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ch_inst,
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umc_inst,
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node_inst);
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}
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}
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const struct amdgpu_ras_block_hw_ops umc_v8_10_ras_hw_ops = {
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.query_ras_error_count = umc_v8_10_query_ras_error_count,
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.query_ras_error_address = umc_v8_10_query_ras_error_address,
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};
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struct amdgpu_umc_ras umc_v8_10_ras = {
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.ras_block = {
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.hw_ops = &umc_v8_10_ras_hw_ops,
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},
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.err_cnt_init = umc_v8_10_err_cnt_init,
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.query_ras_poison_mode = umc_v8_10_query_ras_poison_mode,
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.ecc_info_query_ras_error_count = umc_v8_10_ecc_info_query_ras_error_count,
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.ecc_info_query_ras_error_address = umc_v8_10_ecc_info_query_ras_error_address,
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};
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