715 lines
21 KiB
C
715 lines
21 KiB
C
/*
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* Copyright 2017 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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/*
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* dc_helper.c
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*
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* Created on: Aug 30, 2016
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* Author: agrodzov
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*/
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#include <linux/delay.h>
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#include <linux/stdarg.h>
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#include "dm_services.h"
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#include "dc.h"
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#include "dc_dmub_srv.h"
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#include "reg_helper.h"
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static inline void submit_dmub_read_modify_write(
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struct dc_reg_helper_state *offload,
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const struct dc_context *ctx)
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{
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struct dmub_rb_cmd_read_modify_write *cmd_buf = &offload->cmd_data.read_modify_write;
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bool gather = false;
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offload->should_burst_write =
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(offload->same_addr_count == (DMUB_READ_MODIFY_WRITE_SEQ__MAX - 1));
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cmd_buf->header.payload_bytes =
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sizeof(struct dmub_cmd_read_modify_write_sequence) * offload->reg_seq_count;
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gather = ctx->dmub_srv->reg_helper_offload.gather_in_progress;
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ctx->dmub_srv->reg_helper_offload.gather_in_progress = false;
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dc_dmub_srv_cmd_queue(ctx->dmub_srv, &offload->cmd_data);
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ctx->dmub_srv->reg_helper_offload.gather_in_progress = gather;
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memset(cmd_buf, 0, sizeof(*cmd_buf));
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offload->reg_seq_count = 0;
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offload->same_addr_count = 0;
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}
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static inline void submit_dmub_burst_write(
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struct dc_reg_helper_state *offload,
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const struct dc_context *ctx)
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{
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struct dmub_rb_cmd_burst_write *cmd_buf = &offload->cmd_data.burst_write;
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bool gather = false;
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cmd_buf->header.payload_bytes =
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sizeof(uint32_t) * offload->reg_seq_count;
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gather = ctx->dmub_srv->reg_helper_offload.gather_in_progress;
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ctx->dmub_srv->reg_helper_offload.gather_in_progress = false;
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dc_dmub_srv_cmd_queue(ctx->dmub_srv, &offload->cmd_data);
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ctx->dmub_srv->reg_helper_offload.gather_in_progress = gather;
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memset(cmd_buf, 0, sizeof(*cmd_buf));
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offload->reg_seq_count = 0;
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}
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static inline void submit_dmub_reg_wait(
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struct dc_reg_helper_state *offload,
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const struct dc_context *ctx)
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{
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struct dmub_rb_cmd_reg_wait *cmd_buf = &offload->cmd_data.reg_wait;
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bool gather = false;
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gather = ctx->dmub_srv->reg_helper_offload.gather_in_progress;
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ctx->dmub_srv->reg_helper_offload.gather_in_progress = false;
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dc_dmub_srv_cmd_queue(ctx->dmub_srv, &offload->cmd_data);
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memset(cmd_buf, 0, sizeof(*cmd_buf));
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offload->reg_seq_count = 0;
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ctx->dmub_srv->reg_helper_offload.gather_in_progress = gather;
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}
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struct dc_reg_value_masks {
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uint32_t value;
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uint32_t mask;
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};
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struct dc_reg_sequence {
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uint32_t addr;
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struct dc_reg_value_masks value_masks;
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};
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static inline void set_reg_field_value_masks(
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struct dc_reg_value_masks *field_value_mask,
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uint32_t value,
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uint32_t mask,
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uint8_t shift)
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{
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ASSERT(mask != 0);
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field_value_mask->value = (field_value_mask->value & ~mask) | (mask & (value << shift));
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field_value_mask->mask = field_value_mask->mask | mask;
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}
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static void set_reg_field_values(struct dc_reg_value_masks *field_value_mask,
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uint32_t addr, int n,
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uint8_t shift1, uint32_t mask1, uint32_t field_value1,
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va_list ap)
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{
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uint32_t shift, mask, field_value;
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int i = 1;
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/* gather all bits value/mask getting updated in this register */
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set_reg_field_value_masks(field_value_mask,
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field_value1, mask1, shift1);
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while (i < n) {
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shift = va_arg(ap, uint32_t);
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mask = va_arg(ap, uint32_t);
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field_value = va_arg(ap, uint32_t);
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set_reg_field_value_masks(field_value_mask,
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field_value, mask, shift);
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i++;
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}
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}
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static void dmub_flush_buffer_execute(
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struct dc_reg_helper_state *offload,
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const struct dc_context *ctx)
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{
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submit_dmub_read_modify_write(offload, ctx);
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dc_dmub_srv_cmd_execute(ctx->dmub_srv);
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}
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static void dmub_flush_burst_write_buffer_execute(
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struct dc_reg_helper_state *offload,
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const struct dc_context *ctx)
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{
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submit_dmub_burst_write(offload, ctx);
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dc_dmub_srv_cmd_execute(ctx->dmub_srv);
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}
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static bool dmub_reg_value_burst_set_pack(const struct dc_context *ctx, uint32_t addr,
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uint32_t reg_val)
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{
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struct dc_reg_helper_state *offload = &ctx->dmub_srv->reg_helper_offload;
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struct dmub_rb_cmd_burst_write *cmd_buf = &offload->cmd_data.burst_write;
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/* flush command if buffer is full */
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if (offload->reg_seq_count == DMUB_BURST_WRITE_VALUES__MAX)
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dmub_flush_burst_write_buffer_execute(offload, ctx);
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if (offload->cmd_data.cmd_common.header.type == DMUB_CMD__REG_SEQ_BURST_WRITE &&
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addr != cmd_buf->addr) {
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dmub_flush_burst_write_buffer_execute(offload, ctx);
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return false;
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}
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cmd_buf->header.type = DMUB_CMD__REG_SEQ_BURST_WRITE;
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cmd_buf->header.sub_type = 0;
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cmd_buf->addr = addr;
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cmd_buf->write_values[offload->reg_seq_count] = reg_val;
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offload->reg_seq_count++;
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return true;
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}
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static uint32_t dmub_reg_value_pack(const struct dc_context *ctx, uint32_t addr,
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struct dc_reg_value_masks *field_value_mask)
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{
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struct dc_reg_helper_state *offload = &ctx->dmub_srv->reg_helper_offload;
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struct dmub_rb_cmd_read_modify_write *cmd_buf = &offload->cmd_data.read_modify_write;
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struct dmub_cmd_read_modify_write_sequence *seq;
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/* flush command if buffer is full */
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if (offload->cmd_data.cmd_common.header.type != DMUB_CMD__REG_SEQ_BURST_WRITE &&
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offload->reg_seq_count == DMUB_READ_MODIFY_WRITE_SEQ__MAX)
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dmub_flush_buffer_execute(offload, ctx);
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if (offload->should_burst_write) {
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if (dmub_reg_value_burst_set_pack(ctx, addr, field_value_mask->value))
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return field_value_mask->value;
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else
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offload->should_burst_write = false;
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}
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/* pack commands */
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cmd_buf->header.type = DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE;
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cmd_buf->header.sub_type = 0;
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seq = &cmd_buf->seq[offload->reg_seq_count];
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if (offload->reg_seq_count) {
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if (cmd_buf->seq[offload->reg_seq_count - 1].addr == addr)
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offload->same_addr_count++;
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else
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offload->same_addr_count = 0;
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}
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seq->addr = addr;
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seq->modify_mask = field_value_mask->mask;
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seq->modify_value = field_value_mask->value;
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offload->reg_seq_count++;
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return field_value_mask->value;
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}
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static void dmub_reg_wait_done_pack(const struct dc_context *ctx, uint32_t addr,
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uint32_t mask, uint32_t shift, uint32_t condition_value, uint32_t time_out_us)
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{
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struct dc_reg_helper_state *offload = &ctx->dmub_srv->reg_helper_offload;
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struct dmub_rb_cmd_reg_wait *cmd_buf = &offload->cmd_data.reg_wait;
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cmd_buf->header.type = DMUB_CMD__REG_REG_WAIT;
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cmd_buf->header.sub_type = 0;
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cmd_buf->reg_wait.addr = addr;
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cmd_buf->reg_wait.condition_field_value = mask & (condition_value << shift);
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cmd_buf->reg_wait.mask = mask;
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cmd_buf->reg_wait.time_out_us = time_out_us;
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}
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uint32_t generic_reg_update_ex(const struct dc_context *ctx,
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uint32_t addr, int n,
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uint8_t shift1, uint32_t mask1, uint32_t field_value1,
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...)
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{
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struct dc_reg_value_masks field_value_mask = {0};
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uint32_t reg_val;
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va_list ap;
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va_start(ap, field_value1);
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set_reg_field_values(&field_value_mask, addr, n, shift1, mask1,
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field_value1, ap);
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va_end(ap);
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if (ctx->dmub_srv &&
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ctx->dmub_srv->reg_helper_offload.gather_in_progress)
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return dmub_reg_value_pack(ctx, addr, &field_value_mask);
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/* todo: return void so we can decouple code running in driver from register states */
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/* mmio write directly */
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reg_val = dm_read_reg(ctx, addr);
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reg_val = (reg_val & ~field_value_mask.mask) | field_value_mask.value;
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dm_write_reg(ctx, addr, reg_val);
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return reg_val;
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}
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uint32_t generic_reg_set_ex(const struct dc_context *ctx,
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uint32_t addr, uint32_t reg_val, int n,
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uint8_t shift1, uint32_t mask1, uint32_t field_value1,
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...)
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{
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struct dc_reg_value_masks field_value_mask = {0};
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va_list ap;
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va_start(ap, field_value1);
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set_reg_field_values(&field_value_mask, addr, n, shift1, mask1,
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field_value1, ap);
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va_end(ap);
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/* mmio write directly */
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reg_val = (reg_val & ~field_value_mask.mask) | field_value_mask.value;
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if (ctx->dmub_srv &&
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ctx->dmub_srv->reg_helper_offload.gather_in_progress) {
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return dmub_reg_value_burst_set_pack(ctx, addr, reg_val);
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/* todo: return void so we can decouple code running in driver from register states */
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}
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dm_write_reg(ctx, addr, reg_val);
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return reg_val;
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}
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uint32_t generic_reg_get(const struct dc_context *ctx, uint32_t addr,
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uint8_t shift, uint32_t mask, uint32_t *field_value)
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{
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uint32_t reg_val = dm_read_reg(ctx, addr);
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*field_value = get_reg_field_value_ex(reg_val, mask, shift);
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return reg_val;
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}
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uint32_t generic_reg_get2(const struct dc_context *ctx, uint32_t addr,
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uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
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uint8_t shift2, uint32_t mask2, uint32_t *field_value2)
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{
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uint32_t reg_val = dm_read_reg(ctx, addr);
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*field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1);
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*field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2);
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return reg_val;
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}
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uint32_t generic_reg_get3(const struct dc_context *ctx, uint32_t addr,
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uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
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uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
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uint8_t shift3, uint32_t mask3, uint32_t *field_value3)
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{
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uint32_t reg_val = dm_read_reg(ctx, addr);
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*field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1);
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*field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2);
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*field_value3 = get_reg_field_value_ex(reg_val, mask3, shift3);
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return reg_val;
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}
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uint32_t generic_reg_get4(const struct dc_context *ctx, uint32_t addr,
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uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
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uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
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uint8_t shift3, uint32_t mask3, uint32_t *field_value3,
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uint8_t shift4, uint32_t mask4, uint32_t *field_value4)
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{
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uint32_t reg_val = dm_read_reg(ctx, addr);
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*field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1);
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*field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2);
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*field_value3 = get_reg_field_value_ex(reg_val, mask3, shift3);
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*field_value4 = get_reg_field_value_ex(reg_val, mask4, shift4);
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return reg_val;
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}
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uint32_t generic_reg_get5(const struct dc_context *ctx, uint32_t addr,
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uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
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uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
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uint8_t shift3, uint32_t mask3, uint32_t *field_value3,
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uint8_t shift4, uint32_t mask4, uint32_t *field_value4,
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uint8_t shift5, uint32_t mask5, uint32_t *field_value5)
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{
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uint32_t reg_val = dm_read_reg(ctx, addr);
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*field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1);
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*field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2);
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*field_value3 = get_reg_field_value_ex(reg_val, mask3, shift3);
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*field_value4 = get_reg_field_value_ex(reg_val, mask4, shift4);
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*field_value5 = get_reg_field_value_ex(reg_val, mask5, shift5);
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return reg_val;
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}
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uint32_t generic_reg_get6(const struct dc_context *ctx, uint32_t addr,
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uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
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uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
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uint8_t shift3, uint32_t mask3, uint32_t *field_value3,
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uint8_t shift4, uint32_t mask4, uint32_t *field_value4,
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uint8_t shift5, uint32_t mask5, uint32_t *field_value5,
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uint8_t shift6, uint32_t mask6, uint32_t *field_value6)
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{
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uint32_t reg_val = dm_read_reg(ctx, addr);
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*field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1);
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*field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2);
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*field_value3 = get_reg_field_value_ex(reg_val, mask3, shift3);
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*field_value4 = get_reg_field_value_ex(reg_val, mask4, shift4);
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*field_value5 = get_reg_field_value_ex(reg_val, mask5, shift5);
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*field_value6 = get_reg_field_value_ex(reg_val, mask6, shift6);
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return reg_val;
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}
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uint32_t generic_reg_get7(const struct dc_context *ctx, uint32_t addr,
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uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
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uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
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uint8_t shift3, uint32_t mask3, uint32_t *field_value3,
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uint8_t shift4, uint32_t mask4, uint32_t *field_value4,
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uint8_t shift5, uint32_t mask5, uint32_t *field_value5,
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uint8_t shift6, uint32_t mask6, uint32_t *field_value6,
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uint8_t shift7, uint32_t mask7, uint32_t *field_value7)
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{
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uint32_t reg_val = dm_read_reg(ctx, addr);
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*field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1);
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*field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2);
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*field_value3 = get_reg_field_value_ex(reg_val, mask3, shift3);
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*field_value4 = get_reg_field_value_ex(reg_val, mask4, shift4);
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*field_value5 = get_reg_field_value_ex(reg_val, mask5, shift5);
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*field_value6 = get_reg_field_value_ex(reg_val, mask6, shift6);
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*field_value7 = get_reg_field_value_ex(reg_val, mask7, shift7);
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return reg_val;
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}
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uint32_t generic_reg_get8(const struct dc_context *ctx, uint32_t addr,
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uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
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uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
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uint8_t shift3, uint32_t mask3, uint32_t *field_value3,
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uint8_t shift4, uint32_t mask4, uint32_t *field_value4,
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uint8_t shift5, uint32_t mask5, uint32_t *field_value5,
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uint8_t shift6, uint32_t mask6, uint32_t *field_value6,
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uint8_t shift7, uint32_t mask7, uint32_t *field_value7,
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uint8_t shift8, uint32_t mask8, uint32_t *field_value8)
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{
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uint32_t reg_val = dm_read_reg(ctx, addr);
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*field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1);
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*field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2);
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*field_value3 = get_reg_field_value_ex(reg_val, mask3, shift3);
|
|
*field_value4 = get_reg_field_value_ex(reg_val, mask4, shift4);
|
|
*field_value5 = get_reg_field_value_ex(reg_val, mask5, shift5);
|
|
*field_value6 = get_reg_field_value_ex(reg_val, mask6, shift6);
|
|
*field_value7 = get_reg_field_value_ex(reg_val, mask7, shift7);
|
|
*field_value8 = get_reg_field_value_ex(reg_val, mask8, shift8);
|
|
return reg_val;
|
|
}
|
|
/* note: va version of this is pretty bad idea, since there is a output parameter pass by pointer
|
|
* compiler won't be able to check for size match and is prone to stack corruption type of bugs
|
|
|
|
uint32_t generic_reg_get(const struct dc_context *ctx,
|
|
uint32_t addr, int n, ...)
|
|
{
|
|
uint32_t shift, mask;
|
|
uint32_t *field_value;
|
|
uint32_t reg_val;
|
|
int i = 0;
|
|
|
|
reg_val = dm_read_reg(ctx, addr);
|
|
|
|
va_list ap;
|
|
va_start(ap, n);
|
|
|
|
while (i < n) {
|
|
shift = va_arg(ap, uint32_t);
|
|
mask = va_arg(ap, uint32_t);
|
|
field_value = va_arg(ap, uint32_t *);
|
|
|
|
*field_value = get_reg_field_value_ex(reg_val, mask, shift);
|
|
i++;
|
|
}
|
|
|
|
va_end(ap);
|
|
|
|
return reg_val;
|
|
}
|
|
*/
|
|
|
|
void generic_reg_wait(const struct dc_context *ctx,
|
|
uint32_t addr, uint32_t shift, uint32_t mask, uint32_t condition_value,
|
|
unsigned int delay_between_poll_us, unsigned int time_out_num_tries,
|
|
const char *func_name, int line)
|
|
{
|
|
uint32_t field_value;
|
|
uint32_t reg_val;
|
|
int i;
|
|
|
|
if (ctx->dmub_srv &&
|
|
ctx->dmub_srv->reg_helper_offload.gather_in_progress) {
|
|
dmub_reg_wait_done_pack(ctx, addr, mask, shift, condition_value,
|
|
delay_between_poll_us * time_out_num_tries);
|
|
return;
|
|
}
|
|
|
|
/*
|
|
* Something is terribly wrong if time out is > 3000ms.
|
|
* 3000ms is the maximum time needed for SMU to pass values back.
|
|
* This value comes from experiments.
|
|
*
|
|
*/
|
|
ASSERT(delay_between_poll_us * time_out_num_tries <= 3000000);
|
|
|
|
for (i = 0; i <= time_out_num_tries; i++) {
|
|
if (i) {
|
|
if (delay_between_poll_us >= 1000)
|
|
msleep(delay_between_poll_us/1000);
|
|
else if (delay_between_poll_us > 0)
|
|
udelay(delay_between_poll_us);
|
|
}
|
|
|
|
reg_val = dm_read_reg(ctx, addr);
|
|
|
|
field_value = get_reg_field_value_ex(reg_val, mask, shift);
|
|
|
|
if (field_value == condition_value) {
|
|
if (i * delay_between_poll_us > 1000 &&
|
|
!IS_FPGA_MAXIMUS_DC(ctx->dce_environment))
|
|
DC_LOG_DC("REG_WAIT taking a while: %dms in %s line:%d\n",
|
|
delay_between_poll_us * i / 1000,
|
|
func_name, line);
|
|
return;
|
|
}
|
|
}
|
|
|
|
DC_LOG_WARNING("REG_WAIT timeout %dus * %d tries - %s line:%d\n",
|
|
delay_between_poll_us, time_out_num_tries,
|
|
func_name, line);
|
|
|
|
if (!IS_FPGA_MAXIMUS_DC(ctx->dce_environment))
|
|
BREAK_TO_DEBUGGER();
|
|
}
|
|
|
|
void generic_write_indirect_reg(const struct dc_context *ctx,
|
|
uint32_t addr_index, uint32_t addr_data,
|
|
uint32_t index, uint32_t data)
|
|
{
|
|
dm_write_reg(ctx, addr_index, index);
|
|
dm_write_reg(ctx, addr_data, data);
|
|
}
|
|
|
|
uint32_t generic_read_indirect_reg(const struct dc_context *ctx,
|
|
uint32_t addr_index, uint32_t addr_data,
|
|
uint32_t index)
|
|
{
|
|
uint32_t value = 0;
|
|
|
|
// when reg read, there should not be any offload.
|
|
if (ctx->dmub_srv &&
|
|
ctx->dmub_srv->reg_helper_offload.gather_in_progress) {
|
|
ASSERT(false);
|
|
}
|
|
|
|
dm_write_reg(ctx, addr_index, index);
|
|
value = dm_read_reg(ctx, addr_data);
|
|
|
|
return value;
|
|
}
|
|
|
|
uint32_t generic_indirect_reg_get(const struct dc_context *ctx,
|
|
uint32_t addr_index, uint32_t addr_data,
|
|
uint32_t index, int n,
|
|
uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
|
|
...)
|
|
{
|
|
uint32_t shift, mask, *field_value;
|
|
uint32_t value = 0;
|
|
int i = 1;
|
|
|
|
va_list ap;
|
|
|
|
va_start(ap, field_value1);
|
|
|
|
value = generic_read_indirect_reg(ctx, addr_index, addr_data, index);
|
|
*field_value1 = get_reg_field_value_ex(value, mask1, shift1);
|
|
|
|
while (i < n) {
|
|
shift = va_arg(ap, uint32_t);
|
|
mask = va_arg(ap, uint32_t);
|
|
field_value = va_arg(ap, uint32_t *);
|
|
|
|
*field_value = get_reg_field_value_ex(value, mask, shift);
|
|
i++;
|
|
}
|
|
|
|
va_end(ap);
|
|
|
|
return value;
|
|
}
|
|
|
|
uint32_t generic_indirect_reg_update_ex(const struct dc_context *ctx,
|
|
uint32_t addr_index, uint32_t addr_data,
|
|
uint32_t index, uint32_t reg_val, int n,
|
|
uint8_t shift1, uint32_t mask1, uint32_t field_value1,
|
|
...)
|
|
{
|
|
uint32_t shift, mask, field_value;
|
|
int i = 1;
|
|
|
|
va_list ap;
|
|
|
|
va_start(ap, field_value1);
|
|
|
|
reg_val = set_reg_field_value_ex(reg_val, field_value1, mask1, shift1);
|
|
|
|
while (i < n) {
|
|
shift = va_arg(ap, uint32_t);
|
|
mask = va_arg(ap, uint32_t);
|
|
field_value = va_arg(ap, uint32_t);
|
|
|
|
reg_val = set_reg_field_value_ex(reg_val, field_value, mask, shift);
|
|
i++;
|
|
}
|
|
|
|
generic_write_indirect_reg(ctx, addr_index, addr_data, index, reg_val);
|
|
va_end(ap);
|
|
|
|
return reg_val;
|
|
}
|
|
|
|
|
|
uint32_t generic_indirect_reg_update_ex_sync(const struct dc_context *ctx,
|
|
uint32_t index, uint32_t reg_val, int n,
|
|
uint8_t shift1, uint32_t mask1, uint32_t field_value1,
|
|
...)
|
|
{
|
|
uint32_t shift, mask, field_value;
|
|
int i = 1;
|
|
|
|
va_list ap;
|
|
|
|
va_start(ap, field_value1);
|
|
|
|
reg_val = set_reg_field_value_ex(reg_val, field_value1, mask1, shift1);
|
|
|
|
while (i < n) {
|
|
shift = va_arg(ap, uint32_t);
|
|
mask = va_arg(ap, uint32_t);
|
|
field_value = va_arg(ap, uint32_t);
|
|
|
|
reg_val = set_reg_field_value_ex(reg_val, field_value, mask, shift);
|
|
i++;
|
|
}
|
|
|
|
dm_write_index_reg(ctx, CGS_IND_REG__PCIE, index, reg_val);
|
|
va_end(ap);
|
|
|
|
return reg_val;
|
|
}
|
|
|
|
uint32_t generic_indirect_reg_get_sync(const struct dc_context *ctx,
|
|
uint32_t index, int n,
|
|
uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
|
|
...)
|
|
{
|
|
uint32_t shift, mask, *field_value;
|
|
uint32_t value = 0;
|
|
int i = 1;
|
|
|
|
va_list ap;
|
|
|
|
va_start(ap, field_value1);
|
|
|
|
value = dm_read_index_reg(ctx, CGS_IND_REG__PCIE, index);
|
|
*field_value1 = get_reg_field_value_ex(value, mask1, shift1);
|
|
|
|
while (i < n) {
|
|
shift = va_arg(ap, uint32_t);
|
|
mask = va_arg(ap, uint32_t);
|
|
field_value = va_arg(ap, uint32_t *);
|
|
|
|
*field_value = get_reg_field_value_ex(value, mask, shift);
|
|
i++;
|
|
}
|
|
|
|
va_end(ap);
|
|
|
|
return value;
|
|
}
|
|
|
|
void reg_sequence_start_gather(const struct dc_context *ctx)
|
|
{
|
|
/* if reg sequence is supported and enabled, set flag to
|
|
* indicate we want to have REG_SET, REG_UPDATE macro build
|
|
* reg sequence command buffer rather than MMIO directly.
|
|
*/
|
|
|
|
if (ctx->dmub_srv && ctx->dc->debug.dmub_offload_enabled) {
|
|
struct dc_reg_helper_state *offload =
|
|
&ctx->dmub_srv->reg_helper_offload;
|
|
|
|
/* caller sequence mismatch. need to debug caller. offload will not work!!! */
|
|
ASSERT(!offload->gather_in_progress);
|
|
|
|
offload->gather_in_progress = true;
|
|
}
|
|
}
|
|
|
|
void reg_sequence_start_execute(const struct dc_context *ctx)
|
|
{
|
|
struct dc_reg_helper_state *offload;
|
|
|
|
if (!ctx->dmub_srv)
|
|
return;
|
|
|
|
offload = &ctx->dmub_srv->reg_helper_offload;
|
|
|
|
if (offload && offload->gather_in_progress) {
|
|
offload->gather_in_progress = false;
|
|
offload->should_burst_write = false;
|
|
switch (offload->cmd_data.cmd_common.header.type) {
|
|
case DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE:
|
|
submit_dmub_read_modify_write(offload, ctx);
|
|
break;
|
|
case DMUB_CMD__REG_REG_WAIT:
|
|
submit_dmub_reg_wait(offload, ctx);
|
|
break;
|
|
case DMUB_CMD__REG_SEQ_BURST_WRITE:
|
|
submit_dmub_burst_write(offload, ctx);
|
|
break;
|
|
default:
|
|
return;
|
|
}
|
|
|
|
dc_dmub_srv_cmd_execute(ctx->dmub_srv);
|
|
}
|
|
}
|
|
|
|
void reg_sequence_wait_done(const struct dc_context *ctx)
|
|
{
|
|
/* callback to DM to poll for last submission done*/
|
|
struct dc_reg_helper_state *offload;
|
|
|
|
if (!ctx->dmub_srv)
|
|
return;
|
|
|
|
offload = &ctx->dmub_srv->reg_helper_offload;
|
|
|
|
if (offload &&
|
|
ctx->dc->debug.dmub_offload_enabled &&
|
|
!ctx->dc->debug.dmcub_emulation) {
|
|
dc_dmub_srv_wait_idle(ctx->dmub_srv);
|
|
}
|
|
}
|