313 lines
13 KiB
C
313 lines
13 KiB
C
/* Copyright 2012-15 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#ifndef __DC_MPCC_DCN20_H__
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#define __DC_MPCC_DCN20_H__
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#include "dcn10/dcn10_mpc.h"
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#define TO_DCN20_MPC(mpc_base) \
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container_of(mpc_base, struct dcn20_mpc, base)
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#define MPC_REG_LIST_DCN2_0(inst)\
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MPC_COMMON_REG_LIST_DCN1_0(inst),\
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SRII(MPCC_TOP_GAIN, MPCC, inst),\
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SRII(MPCC_BOT_GAIN_INSIDE, MPCC, inst),\
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SRII(MPCC_BOT_GAIN_OUTSIDE, MPCC, inst),\
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SRII(MPCC_OGAM_RAMA_START_CNTL_B, MPCC_OGAM, inst),\
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SRII(MPCC_OGAM_RAMA_START_CNTL_G, MPCC_OGAM, inst),\
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SRII(MPCC_OGAM_RAMA_START_CNTL_R, MPCC_OGAM, inst),\
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SRII(MPCC_OGAM_RAMA_SLOPE_CNTL_B, MPCC_OGAM, inst),\
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SRII(MPCC_OGAM_RAMA_SLOPE_CNTL_G, MPCC_OGAM, inst),\
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SRII(MPCC_OGAM_RAMA_SLOPE_CNTL_R, MPCC_OGAM, inst),\
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SRII(MPCC_OGAM_RAMA_END_CNTL1_B, MPCC_OGAM, inst),\
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SRII(MPCC_OGAM_RAMA_END_CNTL2_B, MPCC_OGAM, inst),\
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SRII(MPCC_OGAM_RAMA_END_CNTL1_G, MPCC_OGAM, inst),\
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SRII(MPCC_OGAM_RAMA_END_CNTL2_G, MPCC_OGAM, inst),\
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SRII(MPCC_OGAM_RAMA_END_CNTL1_R, MPCC_OGAM, inst),\
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SRII(MPCC_OGAM_RAMA_END_CNTL2_R, MPCC_OGAM, inst),\
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SRII(MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM, inst),\
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SRII(MPCC_OGAM_RAMA_REGION_32_33, MPCC_OGAM, inst),\
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SRII(MPCC_OGAM_RAMB_START_CNTL_B, MPCC_OGAM, inst),\
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SRII(MPCC_OGAM_RAMB_START_CNTL_G, MPCC_OGAM, inst),\
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SRII(MPCC_OGAM_RAMB_START_CNTL_R, MPCC_OGAM, inst),\
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SRII(MPCC_OGAM_RAMB_SLOPE_CNTL_B, MPCC_OGAM, inst),\
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SRII(MPCC_OGAM_RAMB_SLOPE_CNTL_G, MPCC_OGAM, inst),\
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SRII(MPCC_OGAM_RAMB_SLOPE_CNTL_R, MPCC_OGAM, inst),\
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SRII(MPCC_OGAM_RAMB_END_CNTL1_B, MPCC_OGAM, inst),\
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SRII(MPCC_OGAM_RAMB_END_CNTL2_B, MPCC_OGAM, inst),\
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SRII(MPCC_OGAM_RAMB_END_CNTL1_G, MPCC_OGAM, inst),\
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SRII(MPCC_OGAM_RAMB_END_CNTL2_G, MPCC_OGAM, inst),\
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SRII(MPCC_OGAM_RAMB_END_CNTL1_R, MPCC_OGAM, inst),\
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SRII(MPCC_OGAM_RAMB_END_CNTL2_R, MPCC_OGAM, inst),\
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SRII(MPCC_OGAM_RAMB_REGION_0_1, MPCC_OGAM, inst),\
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SRII(MPCC_OGAM_RAMB_REGION_32_33, MPCC_OGAM, inst),\
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SRII(MPCC_MEM_PWR_CTRL, MPCC, inst),\
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SRII(MPCC_OGAM_LUT_INDEX, MPCC_OGAM, inst),\
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SRII(MPCC_OGAM_LUT_RAM_CONTROL, MPCC_OGAM, inst),\
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SRII(MPCC_OGAM_LUT_DATA, MPCC_OGAM, inst),\
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SRII(MPCC_OGAM_MODE, MPCC_OGAM, inst)
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#define MPC_OUT_MUX_REG_LIST_DCN2_0(inst) \
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MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(inst),\
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SRII(CSC_MODE, MPC_OUT, inst),\
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SRII(CSC_C11_C12_A, MPC_OUT, inst),\
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SRII(CSC_C33_C34_A, MPC_OUT, inst),\
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SRII(CSC_C11_C12_B, MPC_OUT, inst),\
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SRII(CSC_C33_C34_B, MPC_OUT, inst),\
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SRII(DENORM_CONTROL, MPC_OUT, inst),\
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SRII(DENORM_CLAMP_G_Y, MPC_OUT, inst),\
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SRII(DENORM_CLAMP_B_CB, MPC_OUT, inst)
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#define MPC_DBG_REG_LIST_DCN2_0() \
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SR(MPC_OCSC_TEST_DEBUG_DATA),\
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SR(MPC_OCSC_TEST_DEBUG_INDEX)
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#define MPC_REG_VARIABLE_LIST_DCN2_0 \
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MPC_COMMON_REG_VARIABLE_LIST \
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uint32_t MPCC_TOP_GAIN[MAX_MPCC]; \
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uint32_t MPCC_BOT_GAIN_INSIDE[MAX_MPCC]; \
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uint32_t MPCC_BOT_GAIN_OUTSIDE[MAX_MPCC]; \
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uint32_t MPCC_OGAM_RAMA_START_CNTL_B[MAX_MPCC]; \
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uint32_t MPCC_OGAM_RAMA_START_CNTL_G[MAX_MPCC]; \
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uint32_t MPCC_OGAM_RAMA_START_CNTL_R[MAX_MPCC]; \
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uint32_t MPCC_OGAM_RAMA_SLOPE_CNTL_B[MAX_MPCC]; \
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uint32_t MPCC_OGAM_RAMA_SLOPE_CNTL_G[MAX_MPCC]; \
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uint32_t MPCC_OGAM_RAMA_SLOPE_CNTL_R[MAX_MPCC]; \
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uint32_t MPCC_OGAM_RAMA_END_CNTL1_B[MAX_MPCC]; \
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uint32_t MPCC_OGAM_RAMA_END_CNTL2_B[MAX_MPCC]; \
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uint32_t MPCC_OGAM_RAMA_END_CNTL1_G[MAX_MPCC]; \
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uint32_t MPCC_OGAM_RAMA_END_CNTL2_G[MAX_MPCC]; \
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uint32_t MPCC_OGAM_RAMA_END_CNTL1_R[MAX_MPCC]; \
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uint32_t MPCC_OGAM_RAMA_END_CNTL2_R[MAX_MPCC]; \
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uint32_t MPCC_OGAM_RAMA_REGION_0_1[MAX_MPCC]; \
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uint32_t MPCC_OGAM_RAMA_REGION_32_33[MAX_MPCC]; \
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uint32_t MPCC_OGAM_RAMB_START_CNTL_B[MAX_MPCC]; \
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uint32_t MPCC_OGAM_RAMB_START_CNTL_G[MAX_MPCC]; \
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uint32_t MPCC_OGAM_RAMB_START_CNTL_R[MAX_MPCC]; \
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uint32_t MPCC_OGAM_RAMB_SLOPE_CNTL_B[MAX_MPCC]; \
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uint32_t MPCC_OGAM_RAMB_SLOPE_CNTL_G[MAX_MPCC]; \
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uint32_t MPCC_OGAM_RAMB_SLOPE_CNTL_R[MAX_MPCC]; \
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uint32_t MPCC_OGAM_RAMB_END_CNTL1_B[MAX_MPCC]; \
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uint32_t MPCC_OGAM_RAMB_END_CNTL2_B[MAX_MPCC]; \
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uint32_t MPCC_OGAM_RAMB_END_CNTL1_G[MAX_MPCC]; \
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uint32_t MPCC_OGAM_RAMB_END_CNTL2_G[MAX_MPCC]; \
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uint32_t MPCC_OGAM_RAMB_END_CNTL1_R[MAX_MPCC]; \
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uint32_t MPCC_OGAM_RAMB_END_CNTL2_R[MAX_MPCC]; \
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uint32_t MPCC_OGAM_RAMB_REGION_0_1[MAX_MPCC]; \
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uint32_t MPCC_OGAM_RAMB_REGION_32_33[MAX_MPCC];\
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uint32_t MPCC_MEM_PWR_CTRL[MAX_MPCC];\
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uint32_t MPCC_OGAM_LUT_INDEX[MAX_MPCC];\
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uint32_t MPCC_OGAM_LUT_RAM_CONTROL[MAX_MPCC];\
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uint32_t MPCC_OGAM_LUT_DATA[MAX_MPCC];\
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uint32_t MPCC_OGAM_MODE[MAX_MPCC];\
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uint32_t MPC_OCSC_TEST_DEBUG_DATA;\
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uint32_t MPC_OCSC_TEST_DEBUG_INDEX;\
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uint32_t CSC_MODE[MAX_OPP]; \
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uint32_t CSC_C11_C12_A[MAX_OPP]; \
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uint32_t CSC_C33_C34_A[MAX_OPP]; \
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uint32_t CSC_C11_C12_B[MAX_OPP]; \
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uint32_t CSC_C33_C34_B[MAX_OPP]; \
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uint32_t DENORM_CONTROL[MAX_OPP]; \
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uint32_t DENORM_CLAMP_G_Y[MAX_OPP]; \
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uint32_t DENORM_CLAMP_B_CB[MAX_OPP];
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#define MPC_COMMON_MASK_SH_LIST_DCN2_0(mask_sh) \
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MPC_COMMON_MASK_SH_LIST_DCN1_0(mask_sh),\
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SF(MPCC0_MPCC_CONTROL, MPCC_BG_BPC, mask_sh),\
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SF(MPCC0_MPCC_CONTROL, MPCC_BOT_GAIN_MODE, mask_sh),\
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SF(MPCC0_MPCC_TOP_GAIN, MPCC_TOP_GAIN, mask_sh),\
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SF(MPCC0_MPCC_BOT_GAIN_INSIDE, MPCC_BOT_GAIN_INSIDE, mask_sh),\
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SF(MPCC0_MPCC_BOT_GAIN_OUTSIDE, MPCC_BOT_GAIN_OUTSIDE, mask_sh),\
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SF(MPC_OCSC_TEST_DEBUG_INDEX, MPC_OCSC_TEST_DEBUG_INDEX, mask_sh),\
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SF(MPC_OUT0_CSC_MODE, MPC_OCSC_MODE, mask_sh),\
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SF(MPC_OUT0_CSC_C11_C12_A, MPC_OCSC_C11_A, mask_sh),\
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SF(MPC_OUT0_CSC_C11_C12_A, MPC_OCSC_C12_A, mask_sh),\
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SF(MPCC0_MPCC_STATUS, MPCC_DISABLED, mask_sh),\
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SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh),\
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SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\
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SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh),\
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SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\
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SF(MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B, MPCC_OGAM_RAMA_EXP_REGION_END_B, mask_sh),\
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SF(MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B, MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B, mask_sh),\
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SF(MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B, MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B, mask_sh),\
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SF(MPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B, mask_sh),\
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SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_B, mask_sh),\
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SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh),\
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SF(MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1, MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET, mask_sh),\
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SF(MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1, MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS, mask_sh),\
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SF(MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1, MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET, mask_sh),\
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SF(MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1, MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS, mask_sh),\
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SF(MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B, MPCC_OGAM_RAMB_EXP_REGION_END_B, mask_sh),\
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SF(MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B, MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B, mask_sh),\
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SF(MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B, MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B, mask_sh),\
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SF(MPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_B, MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B, mask_sh),\
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SF(MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B, MPCC_OGAM_RAMB_EXP_REGION_START_B, mask_sh),\
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SF(MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B, MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B, mask_sh),\
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SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_FORCE, mask_sh),\
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SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_DIS, mask_sh),\
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SF(MPCC_OGAM0_MPCC_OGAM_LUT_INDEX, MPCC_OGAM_LUT_INDEX, mask_sh),\
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SF(MPCC_OGAM0_MPCC_OGAM_LUT_RAM_CONTROL, MPCC_OGAM_LUT_WRITE_EN_MASK, mask_sh),\
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SF(MPCC_OGAM0_MPCC_OGAM_LUT_RAM_CONTROL, MPCC_OGAM_LUT_RAM_SEL, mask_sh),\
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SF(MPCC_OGAM0_MPCC_OGAM_LUT_RAM_CONTROL, MPCC_OGAM_CONFIG_STATUS, mask_sh),\
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SF(MPCC_OGAM0_MPCC_OGAM_LUT_DATA, MPCC_OGAM_LUT_DATA, mask_sh),\
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SF(MPCC_OGAM0_MPCC_OGAM_MODE, MPCC_OGAM_MODE, mask_sh),\
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SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_MODE, mask_sh),\
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SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_CLAMP_MAX_R_CR, mask_sh),\
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SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_CLAMP_MIN_R_CR, mask_sh),\
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SF(MPC_OUT0_DENORM_CLAMP_G_Y, MPC_OUT_DENORM_CLAMP_MAX_G_Y, mask_sh),\
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SF(MPC_OUT0_DENORM_CLAMP_G_Y, MPC_OUT_DENORM_CLAMP_MIN_G_Y, mask_sh),\
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SF(MPC_OUT0_DENORM_CLAMP_B_CB, MPC_OUT_DENORM_CLAMP_MAX_B_CB, mask_sh),\
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SF(MPC_OUT0_DENORM_CLAMP_B_CB, MPC_OUT_DENORM_CLAMP_MIN_B_CB, mask_sh),\
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SF(CUR_VUPDATE_LOCK_SET0, CUR_VUPDATE_LOCK_SET, mask_sh)
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/*
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* DCN2 MPC_OCSC debug status register:
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*
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* Status index including current OCSC Mode is 1
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* OCSC Mode: [1..0]
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*/
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#define MPC_OCSC_TEST_DEBUG_DATA_STATUS_IDX 1
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#define MPC_DEBUG_REG_LIST_SH_DCN20 \
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.MPC_OCSC_TEST_DEBUG_DATA_OCSC_MODE = 0
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#define MPC_DEBUG_REG_LIST_MASK_DCN20 \
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.MPC_OCSC_TEST_DEBUG_DATA_OCSC_MODE = 0x3
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#define MPC_REG_FIELD_LIST_DCN2_0(type) \
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MPC_REG_FIELD_LIST(type)\
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type MPCC_BG_BPC;\
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type MPCC_BOT_GAIN_MODE;\
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type MPCC_TOP_GAIN;\
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type MPCC_BOT_GAIN_INSIDE;\
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type MPCC_BOT_GAIN_OUTSIDE;\
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type MPC_OCSC_TEST_DEBUG_DATA_OCSC_MODE;\
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type MPC_OCSC_TEST_DEBUG_INDEX;\
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type MPC_OCSC_MODE;\
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type MPC_OCSC_C11_A;\
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type MPC_OCSC_C12_A;\
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type MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET;\
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type MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;\
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type MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET;\
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type MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;\
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type MPCC_OGAM_RAMA_EXP_REGION_END_B;\
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type MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B;\
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type MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B;\
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type MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B;\
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type MPCC_OGAM_RAMA_EXP_REGION_START_B;\
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type MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B;\
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type MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET;\
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type MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS;\
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type MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET;\
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type MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS;\
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type MPCC_OGAM_RAMB_EXP_REGION_END_B;\
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type MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B;\
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type MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B;\
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type MPCC_OGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B;\
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type MPCC_OGAM_RAMB_EXP_REGION_START_B;\
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type MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B;\
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type MPCC_OGAM_MEM_PWR_FORCE;\
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type MPCC_OGAM_LUT_INDEX;\
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type MPCC_OGAM_LUT_WRITE_EN_MASK;\
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type MPCC_OGAM_LUT_RAM_SEL;\
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type MPCC_OGAM_CONFIG_STATUS;\
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type MPCC_OGAM_LUT_DATA;\
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type MPCC_OGAM_MODE;\
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type MPC_OUT_DENORM_MODE;\
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type MPC_OUT_DENORM_CLAMP_MAX_R_CR;\
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type MPC_OUT_DENORM_CLAMP_MIN_R_CR;\
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type MPC_OUT_DENORM_CLAMP_MAX_G_Y;\
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type MPC_OUT_DENORM_CLAMP_MIN_G_Y;\
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type MPC_OUT_DENORM_CLAMP_MAX_B_CB;\
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type MPC_OUT_DENORM_CLAMP_MIN_B_CB;\
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type MPCC_DISABLED;\
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type MPCC_OGAM_MEM_PWR_DIS;
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struct dcn20_mpc_registers {
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MPC_REG_VARIABLE_LIST_DCN2_0
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};
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struct dcn20_mpc_shift {
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MPC_REG_FIELD_LIST_DCN2_0(uint8_t)
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};
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struct dcn20_mpc_mask {
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MPC_REG_FIELD_LIST_DCN2_0(uint32_t)
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};
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struct dcn20_mpc {
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struct mpc base;
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int mpcc_in_use_mask;
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int num_mpcc;
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const struct dcn20_mpc_registers *mpc_regs;
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const struct dcn20_mpc_shift *mpc_shift;
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const struct dcn20_mpc_mask *mpc_mask;
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};
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void dcn20_mpc_construct(struct dcn20_mpc *mpcc20,
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struct dc_context *ctx,
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const struct dcn20_mpc_registers *mpc_regs,
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const struct dcn20_mpc_shift *mpc_shift,
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const struct dcn20_mpc_mask *mpc_mask,
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int num_mpcc);
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void mpc2_update_blending(
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struct mpc *mpc,
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struct mpcc_blnd_cfg *blnd_cfg,
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int mpcc_id);
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void mpc2_set_denorm(
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struct mpc *mpc,
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int opp_id,
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enum dc_color_depth output_depth);
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void mpc2_set_denorm_clamp(
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struct mpc *mpc,
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int opp_id,
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struct mpc_denorm_clamp denorm_clamp);
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void mpc2_set_output_csc(
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struct mpc *mpc,
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int opp_id,
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const uint16_t *regval,
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enum mpc_output_csc_mode ocsc_mode);
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void mpc2_set_ocsc_default(
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struct mpc *mpc,
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int opp_id,
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enum dc_color_space color_space,
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enum mpc_output_csc_mode ocsc_mode);
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void mpc2_set_output_gamma(
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struct mpc *mpc,
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int mpcc_id,
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const struct pwl_params *params);
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void mpc2_assert_idle_mpcc(struct mpc *mpc, int id);
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void mpc2_assert_mpcc_idle_before_connect(struct mpc *mpc, int mpcc_id);
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void mpc20_power_on_ogam_lut(struct mpc *mpc, int mpcc_id, bool power_on);
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#endif
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