197 lines
5.6 KiB
C
197 lines
5.6 KiB
C
/*
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* Copyright 2012-15 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#ifndef __DAL_GRPH_OBJECT_DEFS_H__
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#define __DAL_GRPH_OBJECT_DEFS_H__
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#include "grph_object_id.h"
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/* ********************************************************************
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* ********************************************************************
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*
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* These defines shared between All Graphics Objects
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*
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* ********************************************************************
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* ********************************************************************
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*/
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#define MAX_CONNECTOR_NUMBER_PER_SLOT (16)
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#define MAX_BOARD_SLOTS (4)
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#define INVALID_CONNECTOR_INDEX ((unsigned int)(-1))
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/* HPD unit id - HW direct translation */
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enum hpd_source_id {
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HPD_SOURCEID1 = 0,
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HPD_SOURCEID2,
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HPD_SOURCEID3,
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HPD_SOURCEID4,
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HPD_SOURCEID5,
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HPD_SOURCEID6,
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HPD_SOURCEID_COUNT,
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HPD_SOURCEID_UNKNOWN
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};
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/* DDC unit id - HW direct translation */
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enum channel_id {
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CHANNEL_ID_UNKNOWN = 0,
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CHANNEL_ID_DDC1,
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CHANNEL_ID_DDC2,
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CHANNEL_ID_DDC3,
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CHANNEL_ID_DDC4,
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CHANNEL_ID_DDC5,
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CHANNEL_ID_DDC6,
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CHANNEL_ID_DDC_VGA,
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CHANNEL_ID_I2C_PAD,
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CHANNEL_ID_COUNT
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};
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#define DECODE_CHANNEL_ID(ch_id) \
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(ch_id) == CHANNEL_ID_DDC1 ? "CHANNEL_ID_DDC1" : \
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(ch_id) == CHANNEL_ID_DDC2 ? "CHANNEL_ID_DDC2" : \
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(ch_id) == CHANNEL_ID_DDC3 ? "CHANNEL_ID_DDC3" : \
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(ch_id) == CHANNEL_ID_DDC4 ? "CHANNEL_ID_DDC4" : \
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(ch_id) == CHANNEL_ID_DDC5 ? "CHANNEL_ID_DDC5" : \
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(ch_id) == CHANNEL_ID_DDC6 ? "CHANNEL_ID_DDC6" : \
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(ch_id) == CHANNEL_ID_DDC_VGA ? "CHANNEL_ID_DDC_VGA" : \
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(ch_id) == CHANNEL_ID_I2C_PAD ? "CHANNEL_ID_I2C_PAD" : "Invalid"
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enum transmitter {
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TRANSMITTER_UNKNOWN = (-1L),
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TRANSMITTER_UNIPHY_A,
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TRANSMITTER_UNIPHY_B,
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TRANSMITTER_UNIPHY_C,
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TRANSMITTER_UNIPHY_D,
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TRANSMITTER_UNIPHY_E,
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TRANSMITTER_UNIPHY_F,
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TRANSMITTER_NUTMEG_CRT,
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TRANSMITTER_TRAVIS_CRT,
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TRANSMITTER_TRAVIS_LCD,
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TRANSMITTER_UNIPHY_G,
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TRANSMITTER_COUNT
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};
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/* Generic source of the synchronisation input/output signal */
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/* Can be used for flow control, stereo sync, timing sync, frame sync, etc */
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enum sync_source {
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SYNC_SOURCE_NONE = 0,
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/* Source based on controllers */
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SYNC_SOURCE_CONTROLLER0,
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SYNC_SOURCE_CONTROLLER1,
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SYNC_SOURCE_CONTROLLER2,
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SYNC_SOURCE_CONTROLLER3,
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SYNC_SOURCE_CONTROLLER4,
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SYNC_SOURCE_CONTROLLER5,
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/* Source based on GSL group */
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SYNC_SOURCE_GSL_GROUP0,
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SYNC_SOURCE_GSL_GROUP1,
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SYNC_SOURCE_GSL_GROUP2,
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/* Source based on GSL IOs */
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/* These IOs normally used as GSL input/output */
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SYNC_SOURCE_GSL_IO_FIRST,
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SYNC_SOURCE_GSL_IO_GENLOCK_CLOCK = SYNC_SOURCE_GSL_IO_FIRST,
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SYNC_SOURCE_GSL_IO_GENLOCK_VSYNC,
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SYNC_SOURCE_GSL_IO_SWAPLOCK_A,
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SYNC_SOURCE_GSL_IO_SWAPLOCK_B,
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SYNC_SOURCE_GSL_IO_LAST = SYNC_SOURCE_GSL_IO_SWAPLOCK_B,
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/* Source based on regular IOs */
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SYNC_SOURCE_IO_FIRST,
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SYNC_SOURCE_IO_GENERIC_A = SYNC_SOURCE_IO_FIRST,
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SYNC_SOURCE_IO_GENERIC_B,
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SYNC_SOURCE_IO_GENERIC_C,
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SYNC_SOURCE_IO_GENERIC_D,
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SYNC_SOURCE_IO_GENERIC_E,
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SYNC_SOURCE_IO_GENERIC_F,
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SYNC_SOURCE_IO_HPD1,
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SYNC_SOURCE_IO_HPD2,
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SYNC_SOURCE_IO_HSYNC_A,
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SYNC_SOURCE_IO_VSYNC_A,
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SYNC_SOURCE_IO_HSYNC_B,
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SYNC_SOURCE_IO_VSYNC_B,
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SYNC_SOURCE_IO_LAST = SYNC_SOURCE_IO_VSYNC_B,
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/* Misc. flow control sources */
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SYNC_SOURCE_DUAL_GPU_PIN
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};
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enum tx_ffe_id {
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TX_FFE0 = 0,
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TX_FFE1,
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TX_FFE2,
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TX_FFE3,
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TX_FFE_DeEmphasis_Only,
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TX_FFE_PreShoot_Only,
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TX_FFE_No_FFE,
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};
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/* connector sizes in millimeters - from BiosParserTypes.hpp */
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#define CONNECTOR_SIZE_DVI 40
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#define CONNECTOR_SIZE_VGA 32
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#define CONNECTOR_SIZE_HDMI 16
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#define CONNECTOR_SIZE_DP 16
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#define CONNECTOR_SIZE_MINI_DP 9
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#define CONNECTOR_SIZE_UNKNOWN 30
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enum connector_layout_type {
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CONNECTOR_LAYOUT_TYPE_UNKNOWN,
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CONNECTOR_LAYOUT_TYPE_DVI_D,
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CONNECTOR_LAYOUT_TYPE_DVI_I,
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CONNECTOR_LAYOUT_TYPE_VGA,
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CONNECTOR_LAYOUT_TYPE_HDMI,
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CONNECTOR_LAYOUT_TYPE_DP,
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CONNECTOR_LAYOUT_TYPE_MINI_DP,
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};
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struct connector_layout_info {
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struct graphics_object_id connector_id;
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enum connector_layout_type connector_type;
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unsigned int length;
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unsigned int position; /* offset in mm from right side of the board */
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};
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/* length and width in mm */
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struct slot_layout_info {
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unsigned int length;
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unsigned int width;
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unsigned int num_of_connectors;
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struct connector_layout_info connectors[MAX_CONNECTOR_NUMBER_PER_SLOT];
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};
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struct board_layout_info {
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unsigned int num_of_slots;
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/* indicates valid information in bracket layout structure. */
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unsigned int is_number_of_slots_valid : 1;
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unsigned int is_slots_size_valid : 1;
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unsigned int is_connector_offsets_valid : 1;
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unsigned int is_connector_lengths_valid : 1;
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struct slot_layout_info slots[MAX_BOARD_SLOTS];
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};
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#endif
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