381 lines
10 KiB
C
381 lines
10 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (C) 2022 Marek Vasut <marex@denx.de>
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*/
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#include <linux/clk.h>
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#include <linux/media-bus-format.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/of_graph.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <drm/drm_atomic_helper.h>
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#include <drm/drm_bridge.h>
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#include <drm/drm_of.h>
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#include <drm/drm_panel.h>
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#define LDB_CTRL_CH0_ENABLE BIT(0)
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#define LDB_CTRL_CH0_DI_SELECT BIT(1)
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#define LDB_CTRL_CH1_ENABLE BIT(2)
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#define LDB_CTRL_CH1_DI_SELECT BIT(3)
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#define LDB_CTRL_SPLIT_MODE BIT(4)
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#define LDB_CTRL_CH0_DATA_WIDTH BIT(5)
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#define LDB_CTRL_CH0_BIT_MAPPING BIT(6)
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#define LDB_CTRL_CH1_DATA_WIDTH BIT(7)
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#define LDB_CTRL_CH1_BIT_MAPPING BIT(8)
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#define LDB_CTRL_DI0_VSYNC_POLARITY BIT(9)
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#define LDB_CTRL_DI1_VSYNC_POLARITY BIT(10)
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#define LDB_CTRL_REG_CH0_FIFO_RESET BIT(11)
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#define LDB_CTRL_REG_CH1_FIFO_RESET BIT(12)
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#define LDB_CTRL_ASYNC_FIFO_ENABLE BIT(24)
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#define LDB_CTRL_ASYNC_FIFO_THRESHOLD_MASK GENMASK(27, 25)
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#define LVDS_CTRL_CH0_EN BIT(0)
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#define LVDS_CTRL_CH1_EN BIT(1)
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/*
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* LVDS_CTRL_LVDS_EN bit is poorly named in i.MX93 reference manual.
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* Clear it to enable LVDS and set it to disable LVDS.
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*/
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#define LVDS_CTRL_LVDS_EN BIT(1)
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#define LVDS_CTRL_VBG_EN BIT(2)
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#define LVDS_CTRL_HS_EN BIT(3)
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#define LVDS_CTRL_PRE_EMPH_EN BIT(4)
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#define LVDS_CTRL_PRE_EMPH_ADJ(n) (((n) & 0x7) << 5)
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#define LVDS_CTRL_PRE_EMPH_ADJ_MASK GENMASK(7, 5)
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#define LVDS_CTRL_CM_ADJ(n) (((n) & 0x7) << 8)
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#define LVDS_CTRL_CM_ADJ_MASK GENMASK(10, 8)
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#define LVDS_CTRL_CC_ADJ(n) (((n) & 0x7) << 11)
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#define LVDS_CTRL_CC_ADJ_MASK GENMASK(13, 11)
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#define LVDS_CTRL_SLEW_ADJ(n) (((n) & 0x7) << 14)
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#define LVDS_CTRL_SLEW_ADJ_MASK GENMASK(16, 14)
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#define LVDS_CTRL_VBG_ADJ(n) (((n) & 0x7) << 17)
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#define LVDS_CTRL_VBG_ADJ_MASK GENMASK(19, 17)
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enum fsl_ldb_devtype {
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IMX8MP_LDB,
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IMX93_LDB,
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};
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struct fsl_ldb_devdata {
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u32 ldb_ctrl;
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u32 lvds_ctrl;
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bool lvds_en_bit;
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};
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static const struct fsl_ldb_devdata fsl_ldb_devdata[] = {
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[IMX8MP_LDB] = {
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.ldb_ctrl = 0x5c,
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.lvds_ctrl = 0x128,
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},
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[IMX93_LDB] = {
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.ldb_ctrl = 0x20,
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.lvds_ctrl = 0x24,
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.lvds_en_bit = true,
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},
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};
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struct fsl_ldb {
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struct device *dev;
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struct drm_bridge bridge;
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struct drm_bridge *panel_bridge;
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struct clk *clk;
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struct regmap *regmap;
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bool lvds_dual_link;
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const struct fsl_ldb_devdata *devdata;
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};
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static inline struct fsl_ldb *to_fsl_ldb(struct drm_bridge *bridge)
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{
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return container_of(bridge, struct fsl_ldb, bridge);
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}
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static unsigned long fsl_ldb_link_frequency(struct fsl_ldb *fsl_ldb, int clock)
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{
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if (fsl_ldb->lvds_dual_link)
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return clock * 3500;
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else
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return clock * 7000;
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}
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static int fsl_ldb_attach(struct drm_bridge *bridge,
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enum drm_bridge_attach_flags flags)
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{
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struct fsl_ldb *fsl_ldb = to_fsl_ldb(bridge);
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return drm_bridge_attach(bridge->encoder, fsl_ldb->panel_bridge,
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bridge, flags);
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}
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static void fsl_ldb_atomic_enable(struct drm_bridge *bridge,
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struct drm_bridge_state *old_bridge_state)
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{
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struct fsl_ldb *fsl_ldb = to_fsl_ldb(bridge);
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struct drm_atomic_state *state = old_bridge_state->base.state;
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const struct drm_bridge_state *bridge_state;
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const struct drm_crtc_state *crtc_state;
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const struct drm_display_mode *mode;
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struct drm_connector *connector;
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struct drm_crtc *crtc;
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unsigned long configured_link_freq;
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unsigned long requested_link_freq;
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bool lvds_format_24bpp;
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bool lvds_format_jeida;
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u32 reg;
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/* Get the LVDS format from the bridge state. */
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bridge_state = drm_atomic_get_new_bridge_state(state, bridge);
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switch (bridge_state->output_bus_cfg.format) {
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case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
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lvds_format_24bpp = false;
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lvds_format_jeida = true;
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break;
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case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
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lvds_format_24bpp = true;
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lvds_format_jeida = true;
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break;
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case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
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lvds_format_24bpp = true;
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lvds_format_jeida = false;
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break;
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default:
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/*
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* Some bridges still don't set the correct LVDS bus pixel
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* format, use SPWG24 default format until those are fixed.
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*/
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lvds_format_24bpp = true;
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lvds_format_jeida = false;
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dev_warn(fsl_ldb->dev,
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"Unsupported LVDS bus format 0x%04x, please check output bridge driver. Falling back to SPWG24.\n",
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bridge_state->output_bus_cfg.format);
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break;
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}
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/*
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* Retrieve the CRTC adjusted mode. This requires a little dance to go
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* from the bridge to the encoder, to the connector and to the CRTC.
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*/
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connector = drm_atomic_get_new_connector_for_encoder(state,
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bridge->encoder);
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crtc = drm_atomic_get_new_connector_state(state, connector)->crtc;
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crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
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mode = &crtc_state->adjusted_mode;
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requested_link_freq = fsl_ldb_link_frequency(fsl_ldb, mode->clock);
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clk_set_rate(fsl_ldb->clk, requested_link_freq);
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configured_link_freq = clk_get_rate(fsl_ldb->clk);
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if (configured_link_freq != requested_link_freq)
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dev_warn(fsl_ldb->dev, "Configured LDB clock (%lu Hz) does not match requested LVDS clock: %lu Hz",
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configured_link_freq,
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requested_link_freq);
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clk_prepare_enable(fsl_ldb->clk);
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/* Program LDB_CTRL */
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reg = LDB_CTRL_CH0_ENABLE;
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if (fsl_ldb->lvds_dual_link)
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reg |= LDB_CTRL_CH1_ENABLE | LDB_CTRL_SPLIT_MODE;
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if (lvds_format_24bpp) {
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reg |= LDB_CTRL_CH0_DATA_WIDTH;
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if (fsl_ldb->lvds_dual_link)
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reg |= LDB_CTRL_CH1_DATA_WIDTH;
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}
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if (lvds_format_jeida) {
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reg |= LDB_CTRL_CH0_BIT_MAPPING;
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if (fsl_ldb->lvds_dual_link)
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reg |= LDB_CTRL_CH1_BIT_MAPPING;
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}
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if (mode->flags & DRM_MODE_FLAG_PVSYNC) {
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reg |= LDB_CTRL_DI0_VSYNC_POLARITY;
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if (fsl_ldb->lvds_dual_link)
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reg |= LDB_CTRL_DI1_VSYNC_POLARITY;
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}
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regmap_write(fsl_ldb->regmap, fsl_ldb->devdata->ldb_ctrl, reg);
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/* Program LVDS_CTRL */
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reg = LVDS_CTRL_CC_ADJ(2) | LVDS_CTRL_PRE_EMPH_EN |
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LVDS_CTRL_PRE_EMPH_ADJ(3) | LVDS_CTRL_VBG_EN;
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regmap_write(fsl_ldb->regmap, fsl_ldb->devdata->lvds_ctrl, reg);
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/* Wait for VBG to stabilize. */
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usleep_range(15, 20);
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reg |= LVDS_CTRL_CH0_EN;
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if (fsl_ldb->lvds_dual_link)
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reg |= LVDS_CTRL_CH1_EN;
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regmap_write(fsl_ldb->regmap, fsl_ldb->devdata->lvds_ctrl, reg);
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}
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static void fsl_ldb_atomic_disable(struct drm_bridge *bridge,
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struct drm_bridge_state *old_bridge_state)
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{
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struct fsl_ldb *fsl_ldb = to_fsl_ldb(bridge);
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/* Stop channel(s). */
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if (fsl_ldb->devdata->lvds_en_bit)
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/* Set LVDS_CTRL_LVDS_EN bit to disable. */
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regmap_write(fsl_ldb->regmap, fsl_ldb->devdata->lvds_ctrl,
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LVDS_CTRL_LVDS_EN);
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else
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regmap_write(fsl_ldb->regmap, fsl_ldb->devdata->lvds_ctrl, 0);
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regmap_write(fsl_ldb->regmap, fsl_ldb->devdata->ldb_ctrl, 0);
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clk_disable_unprepare(fsl_ldb->clk);
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}
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#define MAX_INPUT_SEL_FORMATS 1
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static u32 *
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fsl_ldb_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
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struct drm_bridge_state *bridge_state,
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struct drm_crtc_state *crtc_state,
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struct drm_connector_state *conn_state,
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u32 output_fmt,
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unsigned int *num_input_fmts)
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{
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u32 *input_fmts;
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*num_input_fmts = 0;
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input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts),
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GFP_KERNEL);
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if (!input_fmts)
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return NULL;
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input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24;
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*num_input_fmts = MAX_INPUT_SEL_FORMATS;
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return input_fmts;
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}
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static enum drm_mode_status
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fsl_ldb_mode_valid(struct drm_bridge *bridge,
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const struct drm_display_info *info,
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const struct drm_display_mode *mode)
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{
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struct fsl_ldb *fsl_ldb = to_fsl_ldb(bridge);
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if (mode->clock > (fsl_ldb->lvds_dual_link ? 160000 : 80000))
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return MODE_CLOCK_HIGH;
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return MODE_OK;
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}
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static const struct drm_bridge_funcs funcs = {
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.attach = fsl_ldb_attach,
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.atomic_enable = fsl_ldb_atomic_enable,
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.atomic_disable = fsl_ldb_atomic_disable,
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.atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
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.atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
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.atomic_get_input_bus_fmts = fsl_ldb_atomic_get_input_bus_fmts,
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.atomic_reset = drm_atomic_helper_bridge_reset,
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.mode_valid = fsl_ldb_mode_valid,
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};
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static int fsl_ldb_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct device_node *panel_node;
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struct device_node *port1, *port2;
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struct drm_panel *panel;
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struct fsl_ldb *fsl_ldb;
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int dual_link;
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fsl_ldb = devm_kzalloc(dev, sizeof(*fsl_ldb), GFP_KERNEL);
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if (!fsl_ldb)
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return -ENOMEM;
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fsl_ldb->devdata = of_device_get_match_data(dev);
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if (!fsl_ldb->devdata)
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return -EINVAL;
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fsl_ldb->dev = &pdev->dev;
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fsl_ldb->bridge.funcs = &funcs;
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fsl_ldb->bridge.of_node = dev->of_node;
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fsl_ldb->clk = devm_clk_get(dev, "ldb");
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if (IS_ERR(fsl_ldb->clk))
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return PTR_ERR(fsl_ldb->clk);
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fsl_ldb->regmap = syscon_node_to_regmap(dev->of_node->parent);
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if (IS_ERR(fsl_ldb->regmap))
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return PTR_ERR(fsl_ldb->regmap);
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/* Locate the panel DT node. */
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panel_node = of_graph_get_remote_node(dev->of_node, 1, 0);
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if (!panel_node)
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return -ENXIO;
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panel = of_drm_find_panel(panel_node);
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of_node_put(panel_node);
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if (IS_ERR(panel))
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return PTR_ERR(panel);
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fsl_ldb->panel_bridge = devm_drm_panel_bridge_add(dev, panel);
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if (IS_ERR(fsl_ldb->panel_bridge))
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return PTR_ERR(fsl_ldb->panel_bridge);
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/* Determine whether this is dual-link configuration */
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port1 = of_graph_get_port_by_id(dev->of_node, 1);
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port2 = of_graph_get_port_by_id(dev->of_node, 2);
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dual_link = drm_of_lvds_get_dual_link_pixel_order(port1, port2);
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of_node_put(port1);
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of_node_put(port2);
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if (dual_link == DRM_LVDS_DUAL_LINK_EVEN_ODD_PIXELS) {
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dev_err(dev, "LVDS channel pixel swap not supported.\n");
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return -EINVAL;
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}
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if (dual_link == DRM_LVDS_DUAL_LINK_ODD_EVEN_PIXELS)
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fsl_ldb->lvds_dual_link = true;
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platform_set_drvdata(pdev, fsl_ldb);
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drm_bridge_add(&fsl_ldb->bridge);
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return 0;
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}
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static int fsl_ldb_remove(struct platform_device *pdev)
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{
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struct fsl_ldb *fsl_ldb = platform_get_drvdata(pdev);
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drm_bridge_remove(&fsl_ldb->bridge);
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return 0;
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}
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static const struct of_device_id fsl_ldb_match[] = {
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{ .compatible = "fsl,imx8mp-ldb",
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.data = &fsl_ldb_devdata[IMX8MP_LDB], },
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{ .compatible = "fsl,imx93-ldb",
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.data = &fsl_ldb_devdata[IMX93_LDB], },
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{ /* sentinel */ },
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};
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MODULE_DEVICE_TABLE(of, fsl_ldb_match);
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static struct platform_driver fsl_ldb_driver = {
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.probe = fsl_ldb_probe,
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.remove = fsl_ldb_remove,
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.driver = {
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.name = "fsl-ldb",
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.of_match_table = fsl_ldb_match,
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},
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};
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module_platform_driver(fsl_ldb_driver);
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MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
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MODULE_DESCRIPTION("Freescale i.MX8MP LDB");
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MODULE_LICENSE("GPL");
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