664 lines
17 KiB
C
664 lines
17 KiB
C
/*
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* Copyright © 2013 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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* Author: Damien Lespiau <damien.lespiau@intel.com>
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*
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*/
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#include <linux/ctype.h>
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#include <linux/debugfs.h>
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#include <linux/seq_file.h>
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#include "i915_irq.h"
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#include "i915_reg.h"
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#include "intel_atomic.h"
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#include "intel_de.h"
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#include "intel_display_types.h"
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#include "intel_pipe_crc.h"
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static const char * const pipe_crc_sources[] = {
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[INTEL_PIPE_CRC_SOURCE_NONE] = "none",
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[INTEL_PIPE_CRC_SOURCE_PLANE1] = "plane1",
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[INTEL_PIPE_CRC_SOURCE_PLANE2] = "plane2",
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[INTEL_PIPE_CRC_SOURCE_PLANE3] = "plane3",
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[INTEL_PIPE_CRC_SOURCE_PLANE4] = "plane4",
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[INTEL_PIPE_CRC_SOURCE_PLANE5] = "plane5",
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[INTEL_PIPE_CRC_SOURCE_PLANE6] = "plane6",
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[INTEL_PIPE_CRC_SOURCE_PLANE7] = "plane7",
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[INTEL_PIPE_CRC_SOURCE_PIPE] = "pipe",
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[INTEL_PIPE_CRC_SOURCE_TV] = "TV",
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[INTEL_PIPE_CRC_SOURCE_DP_B] = "DP-B",
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[INTEL_PIPE_CRC_SOURCE_DP_C] = "DP-C",
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[INTEL_PIPE_CRC_SOURCE_DP_D] = "DP-D",
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[INTEL_PIPE_CRC_SOURCE_AUTO] = "auto",
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};
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static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
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u32 *val)
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{
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if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
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*source = INTEL_PIPE_CRC_SOURCE_PIPE;
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switch (*source) {
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case INTEL_PIPE_CRC_SOURCE_PIPE:
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*val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
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break;
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case INTEL_PIPE_CRC_SOURCE_NONE:
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*val = 0;
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static void i9xx_pipe_crc_auto_source(struct drm_i915_private *dev_priv,
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enum pipe pipe,
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enum intel_pipe_crc_source *source)
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{
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struct intel_encoder *encoder;
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struct intel_crtc *crtc;
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struct intel_digital_port *dig_port;
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*source = INTEL_PIPE_CRC_SOURCE_PIPE;
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drm_modeset_lock_all(&dev_priv->drm);
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for_each_intel_encoder(&dev_priv->drm, encoder) {
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if (!encoder->base.crtc)
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continue;
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crtc = to_intel_crtc(encoder->base.crtc);
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if (crtc->pipe != pipe)
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continue;
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switch (encoder->type) {
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case INTEL_OUTPUT_TVOUT:
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*source = INTEL_PIPE_CRC_SOURCE_TV;
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break;
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case INTEL_OUTPUT_DP:
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case INTEL_OUTPUT_EDP:
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dig_port = enc_to_dig_port(encoder);
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switch (dig_port->base.port) {
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case PORT_B:
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*source = INTEL_PIPE_CRC_SOURCE_DP_B;
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break;
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case PORT_C:
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*source = INTEL_PIPE_CRC_SOURCE_DP_C;
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break;
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case PORT_D:
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*source = INTEL_PIPE_CRC_SOURCE_DP_D;
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break;
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default:
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drm_WARN(&dev_priv->drm, 1, "nonexisting DP port %c\n",
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port_name(dig_port->base.port));
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break;
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}
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break;
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default:
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break;
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}
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}
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drm_modeset_unlock_all(&dev_priv->drm);
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}
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static int vlv_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
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enum pipe pipe,
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enum intel_pipe_crc_source *source,
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u32 *val)
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{
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bool need_stable_symbols = false;
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if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
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i9xx_pipe_crc_auto_source(dev_priv, pipe, source);
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switch (*source) {
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case INTEL_PIPE_CRC_SOURCE_PIPE:
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*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
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break;
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case INTEL_PIPE_CRC_SOURCE_DP_B:
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*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
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need_stable_symbols = true;
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break;
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case INTEL_PIPE_CRC_SOURCE_DP_C:
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*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
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need_stable_symbols = true;
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break;
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case INTEL_PIPE_CRC_SOURCE_DP_D:
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if (!IS_CHERRYVIEW(dev_priv))
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return -EINVAL;
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*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
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need_stable_symbols = true;
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break;
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case INTEL_PIPE_CRC_SOURCE_NONE:
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*val = 0;
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break;
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default:
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return -EINVAL;
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}
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/*
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* When the pipe CRC tap point is after the transcoders we need
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* to tweak symbol-level features to produce a deterministic series of
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* symbols for a given frame. We need to reset those features only once
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* a frame (instead of every nth symbol):
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* - DC-balance: used to ensure a better clock recovery from the data
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* link (SDVO)
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* - DisplayPort scrambling: used for EMI reduction
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*/
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if (need_stable_symbols) {
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u32 tmp = intel_de_read(dev_priv, PORT_DFT2_G4X);
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tmp |= DC_BALANCE_RESET_VLV;
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switch (pipe) {
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case PIPE_A:
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tmp |= PIPE_A_SCRAMBLE_RESET;
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break;
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case PIPE_B:
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tmp |= PIPE_B_SCRAMBLE_RESET;
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break;
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case PIPE_C:
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tmp |= PIPE_C_SCRAMBLE_RESET;
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break;
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default:
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return -EINVAL;
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}
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intel_de_write(dev_priv, PORT_DFT2_G4X, tmp);
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}
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return 0;
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}
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static int i9xx_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
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enum pipe pipe,
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enum intel_pipe_crc_source *source,
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u32 *val)
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{
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if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
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i9xx_pipe_crc_auto_source(dev_priv, pipe, source);
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switch (*source) {
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case INTEL_PIPE_CRC_SOURCE_PIPE:
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*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
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break;
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case INTEL_PIPE_CRC_SOURCE_TV:
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if (!SUPPORTS_TV(dev_priv))
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return -EINVAL;
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*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
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break;
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case INTEL_PIPE_CRC_SOURCE_NONE:
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*val = 0;
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break;
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default:
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/*
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* The DP CRC source doesn't work on g4x.
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* It can be made to work to some degree by selecting
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* the correct CRC source before the port is enabled,
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* and not touching the CRC source bits again until
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* the port is disabled. But even then the bits
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* eventually get stuck and a reboot is needed to get
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* working CRCs on the pipe again. Let's simply
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* refuse to use DP CRCs on g4x.
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*/
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return -EINVAL;
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}
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return 0;
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}
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static void vlv_undo_pipe_scramble_reset(struct drm_i915_private *dev_priv,
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enum pipe pipe)
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{
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u32 tmp = intel_de_read(dev_priv, PORT_DFT2_G4X);
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switch (pipe) {
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case PIPE_A:
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tmp &= ~PIPE_A_SCRAMBLE_RESET;
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break;
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case PIPE_B:
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tmp &= ~PIPE_B_SCRAMBLE_RESET;
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break;
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case PIPE_C:
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tmp &= ~PIPE_C_SCRAMBLE_RESET;
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break;
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default:
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return;
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}
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if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
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tmp &= ~DC_BALANCE_RESET_VLV;
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intel_de_write(dev_priv, PORT_DFT2_G4X, tmp);
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}
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static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
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u32 *val)
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{
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if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
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*source = INTEL_PIPE_CRC_SOURCE_PIPE;
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switch (*source) {
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case INTEL_PIPE_CRC_SOURCE_PLANE1:
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*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
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break;
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case INTEL_PIPE_CRC_SOURCE_PLANE2:
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*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
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break;
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case INTEL_PIPE_CRC_SOURCE_PIPE:
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*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
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break;
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case INTEL_PIPE_CRC_SOURCE_NONE:
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*val = 0;
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static void
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intel_crtc_crc_setup_workarounds(struct intel_crtc *crtc, bool enable)
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{
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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struct intel_crtc_state *pipe_config;
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struct drm_atomic_state *state;
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struct drm_modeset_acquire_ctx ctx;
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int ret;
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drm_modeset_acquire_init(&ctx, 0);
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state = drm_atomic_state_alloc(&dev_priv->drm);
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if (!state) {
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ret = -ENOMEM;
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goto unlock;
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}
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state->acquire_ctx = &ctx;
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retry:
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pipe_config = intel_atomic_get_crtc_state(state, crtc);
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if (IS_ERR(pipe_config)) {
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ret = PTR_ERR(pipe_config);
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goto put_state;
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}
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pipe_config->uapi.mode_changed = pipe_config->has_psr;
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pipe_config->crc_enabled = enable;
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if (IS_HASWELL(dev_priv) &&
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pipe_config->hw.active && crtc->pipe == PIPE_A &&
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pipe_config->cpu_transcoder == TRANSCODER_EDP)
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pipe_config->uapi.mode_changed = true;
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ret = drm_atomic_commit(state);
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put_state:
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if (ret == -EDEADLK) {
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drm_atomic_state_clear(state);
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drm_modeset_backoff(&ctx);
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goto retry;
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}
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drm_atomic_state_put(state);
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unlock:
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drm_WARN(&dev_priv->drm, ret,
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"Toggling workaround to %i returns %i\n", enable, ret);
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drm_modeset_drop_locks(&ctx);
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drm_modeset_acquire_fini(&ctx);
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}
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static int ivb_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
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enum pipe pipe,
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enum intel_pipe_crc_source *source,
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u32 *val)
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{
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if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
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*source = INTEL_PIPE_CRC_SOURCE_PIPE;
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switch (*source) {
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case INTEL_PIPE_CRC_SOURCE_PLANE1:
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*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
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break;
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case INTEL_PIPE_CRC_SOURCE_PLANE2:
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*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
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break;
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case INTEL_PIPE_CRC_SOURCE_PIPE:
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*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
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break;
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case INTEL_PIPE_CRC_SOURCE_NONE:
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*val = 0;
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static int skl_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
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enum pipe pipe,
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enum intel_pipe_crc_source *source,
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u32 *val)
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{
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if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
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*source = INTEL_PIPE_CRC_SOURCE_PIPE;
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switch (*source) {
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case INTEL_PIPE_CRC_SOURCE_PLANE1:
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*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_1_SKL;
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break;
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case INTEL_PIPE_CRC_SOURCE_PLANE2:
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*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_2_SKL;
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break;
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case INTEL_PIPE_CRC_SOURCE_PLANE3:
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*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_3_SKL;
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break;
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case INTEL_PIPE_CRC_SOURCE_PLANE4:
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*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_4_SKL;
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break;
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case INTEL_PIPE_CRC_SOURCE_PLANE5:
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*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_5_SKL;
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break;
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case INTEL_PIPE_CRC_SOURCE_PLANE6:
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*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_6_SKL;
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break;
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case INTEL_PIPE_CRC_SOURCE_PLANE7:
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*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PLANE_7_SKL;
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break;
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case INTEL_PIPE_CRC_SOURCE_PIPE:
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*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DMUX_SKL;
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break;
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case INTEL_PIPE_CRC_SOURCE_NONE:
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*val = 0;
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break;
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default:
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return -EINVAL;
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}
|
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return 0;
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}
|
|
|
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static int get_new_crc_ctl_reg(struct drm_i915_private *dev_priv,
|
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enum pipe pipe,
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enum intel_pipe_crc_source *source, u32 *val)
|
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{
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if (DISPLAY_VER(dev_priv) == 2)
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return i8xx_pipe_crc_ctl_reg(source, val);
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else if (DISPLAY_VER(dev_priv) < 5)
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return i9xx_pipe_crc_ctl_reg(dev_priv, pipe, source, val);
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else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
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return vlv_pipe_crc_ctl_reg(dev_priv, pipe, source, val);
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else if (IS_IRONLAKE(dev_priv) || IS_SANDYBRIDGE(dev_priv))
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return ilk_pipe_crc_ctl_reg(source, val);
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else if (DISPLAY_VER(dev_priv) < 9)
|
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return ivb_pipe_crc_ctl_reg(dev_priv, pipe, source, val);
|
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else
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return skl_pipe_crc_ctl_reg(dev_priv, pipe, source, val);
|
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}
|
|
|
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static int
|
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display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
|
|
{
|
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int i;
|
|
|
|
if (!buf) {
|
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*s = INTEL_PIPE_CRC_SOURCE_NONE;
|
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return 0;
|
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}
|
|
|
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i = match_string(pipe_crc_sources, ARRAY_SIZE(pipe_crc_sources), buf);
|
|
if (i < 0)
|
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return i;
|
|
|
|
*s = i;
|
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return 0;
|
|
}
|
|
|
|
void intel_crtc_crc_init(struct intel_crtc *crtc)
|
|
{
|
|
struct intel_pipe_crc *pipe_crc = &crtc->pipe_crc;
|
|
|
|
spin_lock_init(&pipe_crc->lock);
|
|
}
|
|
|
|
static int i8xx_crc_source_valid(struct drm_i915_private *dev_priv,
|
|
const enum intel_pipe_crc_source source)
|
|
{
|
|
switch (source) {
|
|
case INTEL_PIPE_CRC_SOURCE_PIPE:
|
|
case INTEL_PIPE_CRC_SOURCE_NONE:
|
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return 0;
|
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default:
|
|
return -EINVAL;
|
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}
|
|
}
|
|
|
|
static int i9xx_crc_source_valid(struct drm_i915_private *dev_priv,
|
|
const enum intel_pipe_crc_source source)
|
|
{
|
|
switch (source) {
|
|
case INTEL_PIPE_CRC_SOURCE_PIPE:
|
|
case INTEL_PIPE_CRC_SOURCE_TV:
|
|
case INTEL_PIPE_CRC_SOURCE_NONE:
|
|
return 0;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
}
|
|
|
|
static int vlv_crc_source_valid(struct drm_i915_private *dev_priv,
|
|
const enum intel_pipe_crc_source source)
|
|
{
|
|
switch (source) {
|
|
case INTEL_PIPE_CRC_SOURCE_PIPE:
|
|
case INTEL_PIPE_CRC_SOURCE_DP_B:
|
|
case INTEL_PIPE_CRC_SOURCE_DP_C:
|
|
case INTEL_PIPE_CRC_SOURCE_DP_D:
|
|
case INTEL_PIPE_CRC_SOURCE_NONE:
|
|
return 0;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
}
|
|
|
|
static int ilk_crc_source_valid(struct drm_i915_private *dev_priv,
|
|
const enum intel_pipe_crc_source source)
|
|
{
|
|
switch (source) {
|
|
case INTEL_PIPE_CRC_SOURCE_PIPE:
|
|
case INTEL_PIPE_CRC_SOURCE_PLANE1:
|
|
case INTEL_PIPE_CRC_SOURCE_PLANE2:
|
|
case INTEL_PIPE_CRC_SOURCE_NONE:
|
|
return 0;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
}
|
|
|
|
static int ivb_crc_source_valid(struct drm_i915_private *dev_priv,
|
|
const enum intel_pipe_crc_source source)
|
|
{
|
|
switch (source) {
|
|
case INTEL_PIPE_CRC_SOURCE_PIPE:
|
|
case INTEL_PIPE_CRC_SOURCE_PLANE1:
|
|
case INTEL_PIPE_CRC_SOURCE_PLANE2:
|
|
case INTEL_PIPE_CRC_SOURCE_NONE:
|
|
return 0;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
}
|
|
|
|
static int skl_crc_source_valid(struct drm_i915_private *dev_priv,
|
|
const enum intel_pipe_crc_source source)
|
|
{
|
|
switch (source) {
|
|
case INTEL_PIPE_CRC_SOURCE_PIPE:
|
|
case INTEL_PIPE_CRC_SOURCE_PLANE1:
|
|
case INTEL_PIPE_CRC_SOURCE_PLANE2:
|
|
case INTEL_PIPE_CRC_SOURCE_PLANE3:
|
|
case INTEL_PIPE_CRC_SOURCE_PLANE4:
|
|
case INTEL_PIPE_CRC_SOURCE_PLANE5:
|
|
case INTEL_PIPE_CRC_SOURCE_PLANE6:
|
|
case INTEL_PIPE_CRC_SOURCE_PLANE7:
|
|
case INTEL_PIPE_CRC_SOURCE_NONE:
|
|
return 0;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
}
|
|
|
|
static int
|
|
intel_is_valid_crc_source(struct drm_i915_private *dev_priv,
|
|
const enum intel_pipe_crc_source source)
|
|
{
|
|
if (DISPLAY_VER(dev_priv) == 2)
|
|
return i8xx_crc_source_valid(dev_priv, source);
|
|
else if (DISPLAY_VER(dev_priv) < 5)
|
|
return i9xx_crc_source_valid(dev_priv, source);
|
|
else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
|
|
return vlv_crc_source_valid(dev_priv, source);
|
|
else if (IS_IRONLAKE(dev_priv) || IS_SANDYBRIDGE(dev_priv))
|
|
return ilk_crc_source_valid(dev_priv, source);
|
|
else if (DISPLAY_VER(dev_priv) < 9)
|
|
return ivb_crc_source_valid(dev_priv, source);
|
|
else
|
|
return skl_crc_source_valid(dev_priv, source);
|
|
}
|
|
|
|
const char *const *intel_crtc_get_crc_sources(struct drm_crtc *crtc,
|
|
size_t *count)
|
|
{
|
|
*count = ARRAY_SIZE(pipe_crc_sources);
|
|
return pipe_crc_sources;
|
|
}
|
|
|
|
int intel_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_name,
|
|
size_t *values_cnt)
|
|
{
|
|
struct drm_i915_private *dev_priv = to_i915(crtc->dev);
|
|
enum intel_pipe_crc_source source;
|
|
|
|
if (display_crc_ctl_parse_source(source_name, &source) < 0) {
|
|
drm_dbg(&dev_priv->drm, "unknown source %s\n", source_name);
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (source == INTEL_PIPE_CRC_SOURCE_AUTO ||
|
|
intel_is_valid_crc_source(dev_priv, source) == 0) {
|
|
*values_cnt = 5;
|
|
return 0;
|
|
}
|
|
|
|
return -EINVAL;
|
|
}
|
|
|
|
int intel_crtc_set_crc_source(struct drm_crtc *_crtc, const char *source_name)
|
|
{
|
|
struct intel_crtc *crtc = to_intel_crtc(_crtc);
|
|
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
|
|
struct intel_pipe_crc *pipe_crc = &crtc->pipe_crc;
|
|
enum intel_display_power_domain power_domain;
|
|
enum intel_pipe_crc_source source;
|
|
enum pipe pipe = crtc->pipe;
|
|
intel_wakeref_t wakeref;
|
|
u32 val = 0; /* shut up gcc */
|
|
int ret = 0;
|
|
bool enable;
|
|
|
|
if (display_crc_ctl_parse_source(source_name, &source) < 0) {
|
|
drm_dbg(&dev_priv->drm, "unknown source %s\n", source_name);
|
|
return -EINVAL;
|
|
}
|
|
|
|
power_domain = POWER_DOMAIN_PIPE(pipe);
|
|
wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
|
|
if (!wakeref) {
|
|
drm_dbg_kms(&dev_priv->drm,
|
|
"Trying to capture CRC while pipe is off\n");
|
|
return -EIO;
|
|
}
|
|
|
|
enable = source != INTEL_PIPE_CRC_SOURCE_NONE;
|
|
if (enable)
|
|
intel_crtc_crc_setup_workarounds(crtc, true);
|
|
|
|
ret = get_new_crc_ctl_reg(dev_priv, pipe, &source, &val);
|
|
if (ret != 0)
|
|
goto out;
|
|
|
|
pipe_crc->source = source;
|
|
intel_de_write(dev_priv, PIPE_CRC_CTL(pipe), val);
|
|
intel_de_posting_read(dev_priv, PIPE_CRC_CTL(pipe));
|
|
|
|
if (!source) {
|
|
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
|
|
vlv_undo_pipe_scramble_reset(dev_priv, pipe);
|
|
}
|
|
|
|
pipe_crc->skipped = 0;
|
|
|
|
out:
|
|
if (!enable)
|
|
intel_crtc_crc_setup_workarounds(crtc, false);
|
|
|
|
intel_display_power_put(dev_priv, power_domain, wakeref);
|
|
|
|
return ret;
|
|
}
|
|
|
|
void intel_crtc_enable_pipe_crc(struct intel_crtc *crtc)
|
|
{
|
|
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
|
|
struct intel_pipe_crc *pipe_crc = &crtc->pipe_crc;
|
|
enum pipe pipe = crtc->pipe;
|
|
u32 val = 0;
|
|
|
|
if (!crtc->base.crc.opened)
|
|
return;
|
|
|
|
if (get_new_crc_ctl_reg(dev_priv, pipe, &pipe_crc->source, &val) < 0)
|
|
return;
|
|
|
|
/* Don't need pipe_crc->lock here, IRQs are not generated. */
|
|
pipe_crc->skipped = 0;
|
|
|
|
intel_de_write(dev_priv, PIPE_CRC_CTL(pipe), val);
|
|
intel_de_posting_read(dev_priv, PIPE_CRC_CTL(pipe));
|
|
}
|
|
|
|
void intel_crtc_disable_pipe_crc(struct intel_crtc *crtc)
|
|
{
|
|
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
|
|
struct intel_pipe_crc *pipe_crc = &crtc->pipe_crc;
|
|
enum pipe pipe = crtc->pipe;
|
|
|
|
/* Swallow crc's until we stop generating them. */
|
|
spin_lock_irq(&pipe_crc->lock);
|
|
pipe_crc->skipped = INT_MIN;
|
|
spin_unlock_irq(&pipe_crc->lock);
|
|
|
|
intel_de_write(dev_priv, PIPE_CRC_CTL(pipe), 0);
|
|
intel_de_posting_read(dev_priv, PIPE_CRC_CTL(pipe));
|
|
intel_synchronize_irq(dev_priv);
|
|
}
|