265 lines
8.3 KiB
C
265 lines
8.3 KiB
C
// SPDX-License-Identifier: MIT
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/*
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* Copyright © 2020 Intel Corporation
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*
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*/
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#include "i915_drv.h"
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#include "i915_reg.h"
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#include "intel_de.h"
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#include "intel_display_types.h"
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#include "intel_vrr.h"
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bool intel_vrr_is_capable(struct intel_connector *connector)
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{
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const struct drm_display_info *info = &connector->base.display_info;
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struct drm_i915_private *i915 = to_i915(connector->base.dev);
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struct intel_dp *intel_dp;
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/*
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* DP Sink is capable of VRR video timings if
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* Ignore MSA bit is set in DPCD.
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* EDID monitor range also should be atleast 10 for reasonable
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* Adaptive Sync or Variable Refresh Rate end user experience.
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*/
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switch (connector->base.connector_type) {
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case DRM_MODE_CONNECTOR_eDP:
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if (!connector->panel.vbt.vrr)
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return false;
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fallthrough;
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case DRM_MODE_CONNECTOR_DisplayPort:
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intel_dp = intel_attached_dp(connector);
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if (!drm_dp_sink_can_do_video_without_timing_msa(intel_dp->dpcd))
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return false;
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break;
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default:
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return false;
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}
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return HAS_VRR(i915) &&
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info->monitor_range.max_vfreq - info->monitor_range.min_vfreq > 10;
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}
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void
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intel_vrr_check_modeset(struct intel_atomic_state *state)
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{
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int i;
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struct intel_crtc_state *old_crtc_state, *new_crtc_state;
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struct intel_crtc *crtc;
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for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
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new_crtc_state, i) {
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if (new_crtc_state->uapi.vrr_enabled !=
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old_crtc_state->uapi.vrr_enabled)
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new_crtc_state->uapi.mode_changed = true;
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}
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}
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/*
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* Without VRR registers get latched at:
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* vblank_start
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*
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* With VRR the earliest registers can get latched is:
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* intel_vrr_vmin_vblank_start(), which if we want to maintain
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* the correct min vtotal is >=vblank_start+1
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*
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* The latest point registers can get latched is the vmax decision boundary:
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* intel_vrr_vmax_vblank_start()
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*
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* Between those two points the vblank exit starts (and hence registers get
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* latched) ASAP after a push is sent.
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*
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* framestart_delay is programmable 1-4.
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*/
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static int intel_vrr_vblank_exit_length(const struct intel_crtc_state *crtc_state)
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{
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struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
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struct drm_i915_private *i915 = to_i915(crtc->base.dev);
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if (DISPLAY_VER(i915) >= 13)
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return crtc_state->vrr.guardband;
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else
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/* The hw imposes the extra scanline before frame start */
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return crtc_state->vrr.pipeline_full + crtc_state->framestart_delay + 1;
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}
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int intel_vrr_vmin_vblank_start(const struct intel_crtc_state *crtc_state)
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{
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/* Min vblank actually determined by flipline that is always >=vmin+1 */
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return crtc_state->vrr.vmin + 1 - intel_vrr_vblank_exit_length(crtc_state);
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}
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int intel_vrr_vmax_vblank_start(const struct intel_crtc_state *crtc_state)
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{
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return crtc_state->vrr.vmax - intel_vrr_vblank_exit_length(crtc_state);
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}
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void
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intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
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struct drm_connector_state *conn_state)
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{
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struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
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struct drm_i915_private *i915 = to_i915(crtc->base.dev);
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struct intel_connector *connector =
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to_intel_connector(conn_state->connector);
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struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
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const struct drm_display_info *info = &connector->base.display_info;
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int vmin, vmax;
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if (!intel_vrr_is_capable(connector))
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return;
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if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
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return;
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if (!crtc_state->uapi.vrr_enabled)
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return;
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vmin = DIV_ROUND_UP(adjusted_mode->crtc_clock * 1000,
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adjusted_mode->crtc_htotal * info->monitor_range.max_vfreq);
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vmax = adjusted_mode->crtc_clock * 1000 /
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(adjusted_mode->crtc_htotal * info->monitor_range.min_vfreq);
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vmin = max_t(int, vmin, adjusted_mode->crtc_vtotal);
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vmax = max_t(int, vmax, adjusted_mode->crtc_vtotal);
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if (vmin >= vmax)
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return;
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/*
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* flipline determines the min vblank length the hardware will
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* generate, and flipline>=vmin+1, hence we reduce vmin by one
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* to make sure we can get the actual min vblank length.
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*/
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crtc_state->vrr.vmin = vmin - 1;
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crtc_state->vrr.vmax = vmax;
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crtc_state->vrr.enable = true;
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crtc_state->vrr.flipline = crtc_state->vrr.vmin + 1;
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/*
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* For XE_LPD+, we use guardband and pipeline override
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* is deprecated.
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*/
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if (DISPLAY_VER(i915) >= 13) {
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/*
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* FIXME: Subtract Window2 delay from below value.
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*
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* Window2 specifies time required to program DSB (Window2) in
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* number of scan lines. Assuming 0 for no DSB.
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*/
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crtc_state->vrr.guardband =
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crtc_state->vrr.vmin + 1 - adjusted_mode->crtc_vdisplay;
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} else {
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crtc_state->vrr.pipeline_full =
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min(255, crtc_state->vrr.vmin - adjusted_mode->crtc_vdisplay -
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crtc_state->framestart_delay - 1);
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}
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crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
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}
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static u32 trans_vrr_ctl(const struct intel_crtc_state *crtc_state)
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{
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struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
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if (DISPLAY_VER(i915) >= 13)
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return VRR_CTL_IGN_MAX_SHIFT | VRR_CTL_FLIP_LINE_EN |
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XELPD_VRR_CTL_VRR_GUARDBAND(crtc_state->vrr.guardband);
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else
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return VRR_CTL_IGN_MAX_SHIFT | VRR_CTL_FLIP_LINE_EN |
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VRR_CTL_PIPELINE_FULL(crtc_state->vrr.pipeline_full) |
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VRR_CTL_PIPELINE_FULL_OVERRIDE;
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}
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void intel_vrr_enable(struct intel_encoder *encoder,
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const struct intel_crtc_state *crtc_state)
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{
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struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
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if (!crtc_state->vrr.enable)
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return;
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intel_de_write(dev_priv, TRANS_VRR_VMIN(cpu_transcoder), crtc_state->vrr.vmin - 1);
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intel_de_write(dev_priv, TRANS_VRR_VMAX(cpu_transcoder), crtc_state->vrr.vmax - 1);
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intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder), trans_vrr_ctl(crtc_state));
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intel_de_write(dev_priv, TRANS_VRR_FLIPLINE(cpu_transcoder), crtc_state->vrr.flipline - 1);
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intel_de_write(dev_priv, TRANS_PUSH(cpu_transcoder), TRANS_PUSH_EN);
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intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder),
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VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state));
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}
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void intel_vrr_send_push(const struct intel_crtc_state *crtc_state)
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{
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struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
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if (!crtc_state->vrr.enable)
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return;
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intel_de_write(dev_priv, TRANS_PUSH(cpu_transcoder),
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TRANS_PUSH_EN | TRANS_PUSH_SEND);
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}
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bool intel_vrr_is_push_sent(const struct intel_crtc_state *crtc_state)
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{
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struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
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if (!crtc_state->vrr.enable)
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return false;
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return intel_de_read(dev_priv, TRANS_PUSH(cpu_transcoder)) & TRANS_PUSH_SEND;
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}
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void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
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{
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struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
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if (!old_crtc_state->vrr.enable)
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return;
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intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder),
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trans_vrr_ctl(old_crtc_state));
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intel_de_wait_for_clear(dev_priv, TRANS_VRR_STATUS(cpu_transcoder),
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VRR_STATUS_VRR_EN_LIVE, 1000);
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intel_de_write(dev_priv, TRANS_PUSH(cpu_transcoder), 0);
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intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder), 0);
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}
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void intel_vrr_get_config(struct intel_crtc *crtc,
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struct intel_crtc_state *crtc_state)
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{
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
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u32 trans_vrr_ctl;
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trans_vrr_ctl = intel_de_read(dev_priv, TRANS_VRR_CTL(cpu_transcoder));
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crtc_state->vrr.enable = trans_vrr_ctl & VRR_CTL_VRR_ENABLE;
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if (!crtc_state->vrr.enable)
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return;
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if (DISPLAY_VER(dev_priv) >= 13)
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crtc_state->vrr.guardband =
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REG_FIELD_GET(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, trans_vrr_ctl);
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else
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if (trans_vrr_ctl & VRR_CTL_PIPELINE_FULL_OVERRIDE)
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crtc_state->vrr.pipeline_full =
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REG_FIELD_GET(VRR_CTL_PIPELINE_FULL_MASK, trans_vrr_ctl);
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if (trans_vrr_ctl & VRR_CTL_FLIP_LINE_EN)
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crtc_state->vrr.flipline = intel_de_read(dev_priv, TRANS_VRR_FLIPLINE(cpu_transcoder)) + 1;
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crtc_state->vrr.vmax = intel_de_read(dev_priv, TRANS_VRR_VMAX(cpu_transcoder)) + 1;
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crtc_state->vrr.vmin = intel_de_read(dev_priv, TRANS_VRR_VMIN(cpu_transcoder)) + 1;
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crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
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}
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