446 lines
9.0 KiB
C
446 lines
9.0 KiB
C
/*
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* SPDX-License-Identifier: MIT
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*
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* Copyright © 2019 Intel Corporation
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*/
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#include <linux/kref.h>
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#include "gem/i915_gem_pm.h"
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#include "gt/intel_gt.h"
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#include "i915_selftest.h"
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#include "igt_flush_test.h"
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#include "lib_sw_fence.h"
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#define TEST_OA_CONFIG_UUID "12345678-1234-1234-1234-1234567890ab"
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static int
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alloc_empty_config(struct i915_perf *perf)
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{
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struct i915_oa_config *oa_config;
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oa_config = kzalloc(sizeof(*oa_config), GFP_KERNEL);
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if (!oa_config)
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return -ENOMEM;
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oa_config->perf = perf;
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kref_init(&oa_config->ref);
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strlcpy(oa_config->uuid, TEST_OA_CONFIG_UUID, sizeof(oa_config->uuid));
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mutex_lock(&perf->metrics_lock);
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oa_config->id = idr_alloc(&perf->metrics_idr, oa_config, 2, 0, GFP_KERNEL);
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if (oa_config->id < 0) {
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mutex_unlock(&perf->metrics_lock);
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i915_oa_config_put(oa_config);
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return -ENOMEM;
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}
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mutex_unlock(&perf->metrics_lock);
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return 0;
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}
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static void
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destroy_empty_config(struct i915_perf *perf)
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{
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struct i915_oa_config *oa_config = NULL, *tmp;
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int id;
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mutex_lock(&perf->metrics_lock);
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idr_for_each_entry(&perf->metrics_idr, tmp, id) {
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if (!strcmp(tmp->uuid, TEST_OA_CONFIG_UUID)) {
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oa_config = tmp;
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break;
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}
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}
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if (oa_config)
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idr_remove(&perf->metrics_idr, oa_config->id);
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mutex_unlock(&perf->metrics_lock);
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if (oa_config)
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i915_oa_config_put(oa_config);
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}
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static struct i915_oa_config *
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get_empty_config(struct i915_perf *perf)
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{
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struct i915_oa_config *oa_config = NULL, *tmp;
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int id;
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mutex_lock(&perf->metrics_lock);
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idr_for_each_entry(&perf->metrics_idr, tmp, id) {
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if (!strcmp(tmp->uuid, TEST_OA_CONFIG_UUID)) {
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oa_config = i915_oa_config_get(tmp);
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break;
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}
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}
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mutex_unlock(&perf->metrics_lock);
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return oa_config;
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}
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static struct i915_perf_stream *
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test_stream(struct i915_perf *perf)
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{
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struct drm_i915_perf_open_param param = {};
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struct i915_oa_config *oa_config = get_empty_config(perf);
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struct perf_open_properties props = {
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.engine = intel_engine_lookup_user(perf->i915,
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I915_ENGINE_CLASS_RENDER,
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0),
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.sample_flags = SAMPLE_OA_REPORT,
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.oa_format = GRAPHICS_VER(perf->i915) == 12 ?
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I915_OA_FORMAT_A32u40_A4u32_B8_C8 : I915_OA_FORMAT_C4_B8,
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};
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struct i915_perf_stream *stream;
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struct intel_gt *gt;
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if (!props.engine)
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return NULL;
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gt = props.engine->gt;
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if (!oa_config)
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return NULL;
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props.metrics_set = oa_config->id;
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stream = kzalloc(sizeof(*stream), GFP_KERNEL);
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if (!stream) {
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i915_oa_config_put(oa_config);
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return NULL;
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}
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stream->perf = perf;
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mutex_lock(>->perf.lock);
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if (i915_oa_stream_init(stream, ¶m, &props)) {
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kfree(stream);
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stream = NULL;
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}
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mutex_unlock(>->perf.lock);
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i915_oa_config_put(oa_config);
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return stream;
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}
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static void stream_destroy(struct i915_perf_stream *stream)
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{
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struct intel_gt *gt = stream->engine->gt;
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mutex_lock(>->perf.lock);
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i915_perf_destroy_locked(stream);
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mutex_unlock(>->perf.lock);
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}
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static int live_sanitycheck(void *arg)
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{
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struct drm_i915_private *i915 = arg;
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struct i915_perf_stream *stream;
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/* Quick check we can create a perf stream */
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stream = test_stream(&i915->perf);
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if (!stream)
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return -EINVAL;
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stream_destroy(stream);
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return 0;
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}
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static int write_timestamp(struct i915_request *rq, int slot)
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{
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u32 *cs;
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int len;
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cs = intel_ring_begin(rq, 6);
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if (IS_ERR(cs))
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return PTR_ERR(cs);
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len = 5;
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if (GRAPHICS_VER(rq->engine->i915) >= 8)
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len++;
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*cs++ = GFX_OP_PIPE_CONTROL(len);
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*cs++ = PIPE_CONTROL_GLOBAL_GTT_IVB |
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PIPE_CONTROL_STORE_DATA_INDEX |
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PIPE_CONTROL_WRITE_TIMESTAMP;
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*cs++ = slot * sizeof(u32);
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*cs++ = 0;
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*cs++ = 0;
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*cs++ = 0;
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intel_ring_advance(rq, cs);
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return 0;
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}
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static ktime_t poll_status(struct i915_request *rq, int slot)
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{
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while (!intel_read_status_page(rq->engine, slot) &&
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!i915_request_completed(rq))
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cpu_relax();
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return ktime_get();
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}
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static int live_noa_delay(void *arg)
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{
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struct drm_i915_private *i915 = arg;
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struct i915_perf_stream *stream;
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struct i915_request *rq;
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ktime_t t0, t1;
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u64 expected;
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u32 delay;
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int err;
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int i;
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/* Check that the GPU delays matches expectations */
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stream = test_stream(&i915->perf);
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if (!stream)
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return -ENOMEM;
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expected = atomic64_read(&stream->perf->noa_programming_delay);
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if (stream->engine->class != RENDER_CLASS) {
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err = -ENODEV;
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goto out;
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}
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for (i = 0; i < 4; i++)
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intel_write_status_page(stream->engine, 0x100 + i, 0);
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rq = intel_engine_create_kernel_request(stream->engine);
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if (IS_ERR(rq)) {
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err = PTR_ERR(rq);
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goto out;
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}
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if (rq->engine->emit_init_breadcrumb) {
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err = rq->engine->emit_init_breadcrumb(rq);
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if (err) {
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i915_request_add(rq);
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goto out;
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}
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}
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err = write_timestamp(rq, 0x100);
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if (err) {
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i915_request_add(rq);
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goto out;
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}
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err = rq->engine->emit_bb_start(rq,
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i915_ggtt_offset(stream->noa_wait), 0,
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I915_DISPATCH_SECURE);
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if (err) {
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i915_request_add(rq);
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goto out;
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}
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err = write_timestamp(rq, 0x102);
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if (err) {
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i915_request_add(rq);
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goto out;
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}
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i915_request_get(rq);
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i915_request_add(rq);
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preempt_disable();
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t0 = poll_status(rq, 0x100);
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t1 = poll_status(rq, 0x102);
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preempt_enable();
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pr_info("CPU delay: %lluns, expected %lluns\n",
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ktime_sub(t1, t0), expected);
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delay = intel_read_status_page(stream->engine, 0x102);
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delay -= intel_read_status_page(stream->engine, 0x100);
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delay = intel_gt_clock_interval_to_ns(stream->engine->gt, delay);
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pr_info("GPU delay: %uns, expected %lluns\n",
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delay, expected);
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if (4 * delay < 3 * expected || 2 * delay > 3 * expected) {
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pr_err("GPU delay [%uus] outside of expected threshold! [%lluus, %lluus]\n",
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delay / 1000,
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div_u64(3 * expected, 4000),
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div_u64(3 * expected, 2000));
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err = -EINVAL;
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}
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i915_request_put(rq);
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out:
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stream_destroy(stream);
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return err;
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}
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static int live_noa_gpr(void *arg)
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{
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struct drm_i915_private *i915 = arg;
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struct i915_perf_stream *stream;
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struct intel_context *ce;
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struct i915_request *rq;
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u32 *cs, *store;
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void *scratch;
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u32 gpr0;
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int err;
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int i;
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/* Check that the delay does not clobber user context state (GPR) */
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stream = test_stream(&i915->perf);
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if (!stream)
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return -ENOMEM;
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gpr0 = i915_mmio_reg_offset(GEN8_RING_CS_GPR(stream->engine->mmio_base, 0));
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ce = intel_context_create(stream->engine);
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if (IS_ERR(ce)) {
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err = PTR_ERR(ce);
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goto out;
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}
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/* Poison the ce->vm so we detect writes not to the GGTT gt->scratch */
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scratch = __px_vaddr(ce->vm->scratch[0]);
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memset(scratch, POISON_FREE, PAGE_SIZE);
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rq = intel_context_create_request(ce);
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if (IS_ERR(rq)) {
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err = PTR_ERR(rq);
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goto out_ce;
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}
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i915_request_get(rq);
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if (rq->engine->emit_init_breadcrumb) {
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err = rq->engine->emit_init_breadcrumb(rq);
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if (err) {
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i915_request_add(rq);
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goto out_rq;
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}
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}
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/* Fill the 16 qword [32 dword] GPR with a known unlikely value */
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cs = intel_ring_begin(rq, 2 * 32 + 2);
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if (IS_ERR(cs)) {
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err = PTR_ERR(cs);
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i915_request_add(rq);
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goto out_rq;
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}
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*cs++ = MI_LOAD_REGISTER_IMM(32);
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for (i = 0; i < 32; i++) {
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*cs++ = gpr0 + i * sizeof(u32);
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*cs++ = STACK_MAGIC;
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}
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*cs++ = MI_NOOP;
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intel_ring_advance(rq, cs);
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/* Execute the GPU delay */
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err = rq->engine->emit_bb_start(rq,
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i915_ggtt_offset(stream->noa_wait), 0,
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I915_DISPATCH_SECURE);
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if (err) {
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i915_request_add(rq);
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goto out_rq;
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}
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/* Read the GPR back, using the pinned global HWSP for convenience */
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store = memset32(rq->engine->status_page.addr + 512, 0, 32);
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for (i = 0; i < 32; i++) {
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u32 cmd;
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cs = intel_ring_begin(rq, 4);
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if (IS_ERR(cs)) {
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err = PTR_ERR(cs);
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i915_request_add(rq);
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goto out_rq;
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}
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cmd = MI_STORE_REGISTER_MEM;
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if (GRAPHICS_VER(i915) >= 8)
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cmd++;
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cmd |= MI_USE_GGTT;
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*cs++ = cmd;
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*cs++ = gpr0 + i * sizeof(u32);
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*cs++ = i915_ggtt_offset(rq->engine->status_page.vma) +
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offset_in_page(store) +
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i * sizeof(u32);
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*cs++ = 0;
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intel_ring_advance(rq, cs);
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}
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i915_request_add(rq);
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if (i915_request_wait(rq, I915_WAIT_INTERRUPTIBLE, HZ / 2) < 0) {
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pr_err("noa_wait timed out\n");
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intel_gt_set_wedged(stream->engine->gt);
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err = -EIO;
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goto out_rq;
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}
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/* Verify that the GPR contain our expected values */
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for (i = 0; i < 32; i++) {
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if (store[i] == STACK_MAGIC)
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continue;
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pr_err("GPR[%d] lost, found:%08x, expected:%08x!\n",
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i, store[i], STACK_MAGIC);
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err = -EINVAL;
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}
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/* Verify that the user's scratch page was not used for GPR storage */
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if (memchr_inv(scratch, POISON_FREE, PAGE_SIZE)) {
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pr_err("Scratch page overwritten!\n");
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igt_hexdump(scratch, 4096);
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err = -EINVAL;
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}
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out_rq:
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i915_request_put(rq);
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out_ce:
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intel_context_put(ce);
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out:
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stream_destroy(stream);
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return err;
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}
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int i915_perf_live_selftests(struct drm_i915_private *i915)
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{
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static const struct i915_subtest tests[] = {
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SUBTEST(live_sanitycheck),
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SUBTEST(live_noa_delay),
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SUBTEST(live_noa_gpr),
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};
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struct i915_perf *perf = &i915->perf;
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int err;
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if (!perf->metrics_kobj || !perf->ops.enable_metric_set)
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return 0;
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if (intel_gt_is_wedged(to_gt(i915)))
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return 0;
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err = alloc_empty_config(&i915->perf);
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if (err)
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return err;
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err = i915_live_subtests(tests, i915);
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destroy_empty_config(&i915->perf);
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return err;
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}
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