388 lines
9.3 KiB
C
388 lines
9.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only
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*
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* Copyright © 2019-2020 Intel Corporation
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*/
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#ifndef __KMB_DSI_H__
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#define __KMB_DSI_H__
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#include <drm/drm_encoder.h>
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#include <drm/drm_mipi_dsi.h>
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/* MIPI TX CFG */
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#define MIPI_TX_LANE_DATA_RATE_MBPS 891
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#define MIPI_TX_REF_CLK_KHZ 24000
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#define MIPI_TX_CFG_CLK_KHZ 24000
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#define MIPI_TX_BPP 24
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/* DPHY Tx test codes*/
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#define TEST_CODE_FSM_CONTROL 0x03
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#define TEST_CODE_MULTIPLE_PHY_CTRL 0x0C
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#define TEST_CODE_PLL_PROPORTIONAL_CHARGE_PUMP_CTRL 0x0E
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#define TEST_CODE_PLL_INTEGRAL_CHARGE_PUMP_CTRL 0x0F
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#define TEST_CODE_PLL_VCO_CTRL 0x12
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#define TEST_CODE_PLL_GMP_CTRL 0x13
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#define TEST_CODE_PLL_PHASE_ERR_CTRL 0x14
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#define TEST_CODE_PLL_LOCK_FILTER 0x15
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#define TEST_CODE_PLL_UNLOCK_FILTER 0x16
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#define TEST_CODE_PLL_INPUT_DIVIDER 0x17
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#define TEST_CODE_PLL_FEEDBACK_DIVIDER 0x18
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#define PLL_FEEDBACK_DIVIDER_HIGH BIT(7)
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#define TEST_CODE_PLL_OUTPUT_CLK_SEL 0x19
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#define PLL_N_OVR_EN BIT(4)
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#define PLL_M_OVR_EN BIT(5)
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#define TEST_CODE_VOD_LEVEL 0x24
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#define TEST_CODE_PLL_CHARGE_PUMP_BIAS 0x1C
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#define TEST_CODE_PLL_LOCK_DETECTOR 0x1D
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#define TEST_CODE_HS_FREQ_RANGE_CFG 0x44
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#define TEST_CODE_PLL_ANALOG_PROG 0x1F
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#define TEST_CODE_SLEW_RATE_OVERRIDE_CTRL 0xA0
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#define TEST_CODE_SLEW_RATE_DDL_LOOP_CTRL 0xA3
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#define TEST_CODE_SLEW_RATE_DDL_CYCLES 0xA4
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/* DPHY params */
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#define PLL_N_MIN 0
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#define PLL_N_MAX 15
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#define PLL_M_MIN 62
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#define PLL_M_MAX 623
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#define PLL_FVCO_MAX 1250
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#define TIMEOUT 600
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#define MIPI_TX_FRAME_GEN 4
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#define MIPI_TX_FRAME_GEN_SECTIONS 4
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#define MIPI_CTRL_VIRTUAL_CHANNELS 4
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#define MIPI_D_LANES_PER_DPHY 2
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#define MIPI_CTRL_2LANE_MAX_MC_FIFO_LOC 255
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#define MIPI_CTRL_4LANE_MAX_MC_FIFO_LOC 511
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/* 2 Data Lanes per D-PHY */
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#define MIPI_DPHY_D_LANES 2
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#define MIPI_DPHY_DEFAULT_BIT_RATES 63
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#define KMB_MIPI_DEFAULT_CLK 24000000
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#define KMB_MIPI_DEFAULT_CFG_CLK 24000000
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#define to_kmb_dsi(x) container_of(x, struct kmb_dsi, base)
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struct kmb_dsi {
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struct drm_encoder base;
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struct device *dev;
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struct platform_device *pdev;
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struct mipi_dsi_host *host;
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struct mipi_dsi_device *device;
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struct drm_bridge *adv_bridge;
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void __iomem *mipi_mmio;
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struct clk *clk_mipi;
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struct clk *clk_mipi_ecfg;
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struct clk *clk_mipi_cfg;
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int sys_clk_mhz;
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};
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/* DPHY Tx test codes */
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enum mipi_ctrl_num {
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MIPI_CTRL0 = 0,
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MIPI_CTRL1,
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MIPI_CTRL2,
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MIPI_CTRL3,
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MIPI_CTRL4,
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MIPI_CTRL5,
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MIPI_CTRL6,
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MIPI_CTRL7,
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MIPI_CTRL8,
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MIPI_CTRL9,
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MIPI_CTRL_NA
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};
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enum mipi_dphy_num {
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MIPI_DPHY0 = 0,
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MIPI_DPHY1,
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MIPI_DPHY2,
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MIPI_DPHY3,
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MIPI_DPHY4,
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MIPI_DPHY5,
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MIPI_DPHY6,
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MIPI_DPHY7,
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MIPI_DPHY8,
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MIPI_DPHY9,
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MIPI_DPHY_NA
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};
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enum mipi_dir {
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MIPI_RX,
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MIPI_TX
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};
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enum mipi_ctrl_type {
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MIPI_DSI,
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MIPI_CSI
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};
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enum mipi_data_if {
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MIPI_IF_DMA,
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MIPI_IF_PARALLEL
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};
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enum mipi_data_mode {
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MIPI_DATA_MODE0,
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MIPI_DATA_MODE1,
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MIPI_DATA_MODE2,
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MIPI_DATA_MODE3
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};
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enum mipi_dsi_video_mode {
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DSI_VIDEO_MODE_NO_BURST_PULSE,
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DSI_VIDEO_MODE_NO_BURST_EVENT,
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DSI_VIDEO_MODE_BURST
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};
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enum mipi_dsi_blanking_mode {
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TRANSITION_TO_LOW_POWER,
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SEND_BLANK_PACKET
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};
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enum mipi_dsi_eotp {
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DSI_EOTP_DISABLED,
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DSI_EOTP_ENABLES
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};
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enum mipi_dsi_data_type {
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DSI_SP_DT_RESERVED_00 = 0x00,
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DSI_SP_DT_VSYNC_START = 0x01,
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DSI_SP_DT_COLOR_MODE_OFF = 0x02,
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DSI_SP_DT_GENERIC_SHORT_WR = 0x03,
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DSI_SP_DT_GENERIC_RD = 0x04,
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DSI_SP_DT_DCS_SHORT_WR = 0x05,
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DSI_SP_DT_DCS_RD = 0x06,
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DSI_SP_DT_EOTP = 0x08,
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DSI_LP_DT_NULL = 0x09,
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DSI_LP_DT_RESERVED_0A = 0x0a,
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DSI_LP_DT_RESERVED_0B = 0x0b,
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DSI_LP_DT_LPPS_YCBCR422_20B = 0x0c,
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DSI_LP_DT_PPS_RGB101010_30B = 0x0d,
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DSI_LP_DT_PPS_RGB565_16B = 0x0e,
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DSI_LP_DT_RESERVED_0F = 0x0f,
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DSI_SP_DT_RESERVED_10 = 0x10,
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DSI_SP_DT_VSYNC_END = 0x11,
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DSI_SP_DT_COLOR_MODE_ON = 0x12,
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DSI_SP_DT_GENERIC_SHORT_WR_1PAR = 0x13,
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DSI_SP_DT_GENERIC_RD_1PAR = 0x14,
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DSI_SP_DT_DCS_SHORT_WR_1PAR = 0x15,
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DSI_SP_DT_RESERVED_16 = 0x16,
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DSI_SP_DT_RESERVED_17 = 0x17,
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DSI_SP_DT_RESERVED_18 = 0x18,
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DSI_LP_DT_BLANK = 0x19,
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DSI_LP_DT_RESERVED_1A = 0x1a,
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DSI_LP_DT_RESERVED_1B = 0x1b,
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DSI_LP_DT_PPS_YCBCR422_24B = 0x1c,
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DSI_LP_DT_PPS_RGB121212_36B = 0x1d,
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DSI_LP_DT_PPS_RGB666_18B = 0x1e,
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DSI_LP_DT_RESERVED_1F = 0x1f,
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DSI_SP_DT_RESERVED_20 = 0x20,
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DSI_SP_DT_HSYNC_START = 0x21,
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DSI_SP_DT_SHUT_DOWN_PERIPH_CMD = 0x22,
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DSI_SP_DT_GENERIC_SHORT_WR_2PAR = 0x23,
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DSI_SP_DT_GENERIC_RD_2PAR = 0x24,
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DSI_SP_DT_RESERVED_25 = 0x25,
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DSI_SP_DT_RESERVED_26 = 0x26,
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DSI_SP_DT_RESERVED_27 = 0x27,
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DSI_SP_DT_RESERVED_28 = 0x28,
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DSI_LP_DT_GENERIC_LONG_WR = 0x29,
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DSI_LP_DT_RESERVED_2A = 0x2a,
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DSI_LP_DT_RESERVED_2B = 0x2b,
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DSI_LP_DT_PPS_YCBCR422_16B = 0x2c,
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DSI_LP_DT_RESERVED_2D = 0x2d,
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DSI_LP_DT_LPPS_RGB666_18B = 0x2e,
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DSI_LP_DT_RESERVED_2F = 0x2f,
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DSI_SP_DT_RESERVED_30 = 0x30,
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DSI_SP_DT_HSYNC_END = 0x31,
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DSI_SP_DT_TURN_ON_PERIPH_CMD = 0x32,
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DSI_SP_DT_RESERVED_33 = 0x33,
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DSI_SP_DT_RESERVED_34 = 0x34,
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DSI_SP_DT_RESERVED_35 = 0x35,
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DSI_SP_DT_RESERVED_36 = 0x36,
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DSI_SP_DT_SET_MAX_RETURN_PKT_SIZE = 0x37,
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DSI_SP_DT_RESERVED_38 = 0x38,
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DSI_LP_DT_DSC_LONG_WR = 0x39,
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DSI_LP_DT_RESERVED_3A = 0x3a,
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DSI_LP_DT_RESERVED_3B = 0x3b,
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DSI_LP_DT_RESERVED_3C = 0x3c,
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DSI_LP_DT_PPS_YCBCR420_12B = 0x3d,
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DSI_LP_DT_PPS_RGB888_24B = 0x3e,
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DSI_LP_DT_RESERVED_3F = 0x3f
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};
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enum mipi_tx_hs_tp_sel {
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MIPI_TX_HS_TP_WHOLE_FRAME_COLOR0 = 0,
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MIPI_TX_HS_TP_WHOLE_FRAME_COLOR1,
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MIPI_TX_HS_TP_V_STRIPES,
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MIPI_TX_HS_TP_H_STRIPES,
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};
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enum dphy_mode {
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MIPI_DPHY_SLAVE = 0,
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MIPI_DPHY_MASTER
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};
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enum dphy_tx_fsm {
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DPHY_TX_POWERDWN = 0,
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DPHY_TX_BGPON,
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DPHY_TX_TERMCAL,
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DPHY_TX_TERMCALUP,
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DPHY_TX_OFFSETCAL,
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DPHY_TX_LOCK,
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DPHY_TX_SRCAL,
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DPHY_TX_IDLE,
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DPHY_TX_ULP,
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DPHY_TX_LANESTART,
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DPHY_TX_CLKALIGN,
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DPHY_TX_DDLTUNNING,
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DPHY_TX_ULP_FORCE_PLL,
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DPHY_TX_LOCK_LOSS
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};
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struct mipi_data_type_params {
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u8 size_constraint_pixels;
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u8 size_constraint_bytes;
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u8 pixels_per_pclk;
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u8 bits_per_pclk;
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};
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struct mipi_tx_dsi_cfg {
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u8 hfp_blank_en; /* Horizontal front porch blanking enable */
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u8 eotp_en; /* End of transmission packet enable */
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/* Last vertical front porch blanking mode */
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u8 lpm_last_vfp_line;
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/* First vertical sync active blanking mode */
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u8 lpm_first_vsa_line;
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u8 sync_pulse_eventn; /* Sync type */
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u8 hfp_blanking; /* Horizontal front porch blanking mode */
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u8 hbp_blanking; /* Horizontal back porch blanking mode */
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u8 hsa_blanking; /* Horizontal sync active blanking mode */
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u8 v_blanking; /* Vertical timing blanking mode */
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};
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struct mipi_tx_frame_section_cfg {
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u32 dma_v_stride;
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u16 dma_v_scale_cfg;
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u16 width_pixels;
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u16 height_lines;
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u8 dma_packed;
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u8 bpp;
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u8 bpp_unpacked;
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u8 dma_h_stride;
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u8 data_type;
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u8 data_mode;
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u8 dma_flip_rotate_sel;
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};
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struct mipi_tx_frame_timing_cfg {
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u32 bpp;
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u32 lane_rate_mbps;
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u32 hsync_width;
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u32 h_backporch;
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u32 h_frontporch;
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u32 h_active;
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u16 vsync_width;
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u16 v_backporch;
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u16 v_frontporch;
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u16 v_active;
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u8 active_lanes;
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};
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struct mipi_tx_frame_sect_phcfg {
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u32 wc;
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enum mipi_data_mode data_mode;
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enum mipi_dsi_data_type data_type;
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u8 vchannel;
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u8 dma_packed;
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};
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struct mipi_tx_frame_cfg {
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struct mipi_tx_frame_section_cfg *sections[MIPI_TX_FRAME_GEN_SECTIONS];
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u32 hsync_width; /* in pixels */
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u32 h_backporch; /* in pixels */
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u32 h_frontporch; /* in pixels */
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u16 vsync_width; /* in lines */
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u16 v_backporch; /* in lines */
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u16 v_frontporch; /* in lines */
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};
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struct mipi_tx_ctrl_cfg {
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struct mipi_tx_frame_cfg *frames[MIPI_TX_FRAME_GEN];
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const struct mipi_tx_dsi_cfg *tx_dsi_cfg;
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u8 line_sync_pkt_en;
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u8 line_counter_active;
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u8 frame_counter_active;
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u8 tx_hsclkkidle_cnt;
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u8 tx_hsexit_cnt;
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u8 tx_crc_en;
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u8 tx_hact_wait_stop;
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u8 tx_always_use_hact;
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u8 tx_wait_trig;
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u8 tx_wait_all_sect;
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};
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/* configuration structure for MIPI control */
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struct mipi_ctrl_cfg {
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u8 active_lanes; /* # active lanes per controller 2/4 */
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u32 lane_rate_mbps; /* MBPS */
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u32 ref_clk_khz;
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u32 cfg_clk_khz;
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struct mipi_tx_ctrl_cfg tx_ctrl_cfg;
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};
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static inline void kmb_write_mipi(struct kmb_dsi *kmb_dsi,
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unsigned int reg, u32 value)
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{
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writel(value, (kmb_dsi->mipi_mmio + reg));
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}
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static inline u32 kmb_read_mipi(struct kmb_dsi *kmb_dsi, unsigned int reg)
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{
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return readl(kmb_dsi->mipi_mmio + reg);
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}
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static inline void kmb_write_bits_mipi(struct kmb_dsi *kmb_dsi,
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unsigned int reg, u32 offset,
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u32 num_bits, u32 value)
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{
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u32 reg_val = kmb_read_mipi(kmb_dsi, reg);
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u32 mask = (1 << num_bits) - 1;
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value &= mask;
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mask <<= offset;
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reg_val &= (~mask);
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reg_val |= (value << offset);
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kmb_write_mipi(kmb_dsi, reg, reg_val);
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}
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static inline void kmb_set_bit_mipi(struct kmb_dsi *kmb_dsi,
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unsigned int reg, u32 offset)
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{
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u32 reg_val = kmb_read_mipi(kmb_dsi, reg);
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kmb_write_mipi(kmb_dsi, reg, reg_val | (1 << offset));
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}
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static inline void kmb_clr_bit_mipi(struct kmb_dsi *kmb_dsi,
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unsigned int reg, u32 offset)
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{
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u32 reg_val = kmb_read_mipi(kmb_dsi, reg);
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kmb_write_mipi(kmb_dsi, reg, reg_val & (~(1 << offset)));
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}
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int kmb_dsi_host_bridge_init(struct device *dev);
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struct kmb_dsi *kmb_dsi_init(struct platform_device *pdev);
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void kmb_dsi_host_unregister(struct kmb_dsi *kmb_dsi);
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int kmb_dsi_mode_set(struct kmb_dsi *kmb_dsi, struct drm_display_mode *mode,
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int sys_clk_mhz, struct drm_atomic_state *old_state);
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int kmb_dsi_map_mmio(struct kmb_dsi *kmb_dsi);
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int kmb_dsi_clk_init(struct kmb_dsi *kmb_dsi);
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int kmb_dsi_encoder_init(struct drm_device *dev, struct kmb_dsi *kmb_dsi);
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#endif /* __KMB_DSI_H__ */
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