321 lines
8.9 KiB
C
321 lines
8.9 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2021 MediaTek Inc.
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*/
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#include <linux/clk.h>
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#include <linux/component.h>
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#include <linux/of_device.h>
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#include <linux/of_irq.h>
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#include <linux/platform_device.h>
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#include <linux/reset.h>
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#include <linux/soc/mediatek/mtk-cmdq.h>
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#include "mtk_drm_ddp_comp.h"
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#include "mtk_drm_drv.h"
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#include "mtk_disp_drv.h"
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#define DISP_REG_MERGE_CTRL 0x000
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#define MERGE_EN 1
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#define DISP_REG_MERGE_CFG_0 0x010
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#define DISP_REG_MERGE_CFG_1 0x014
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#define DISP_REG_MERGE_CFG_4 0x020
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#define DISP_REG_MERGE_CFG_10 0x038
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/* no swap */
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#define SWAP_MODE 0
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#define FLD_SWAP_MODE GENMASK(4, 0)
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#define DISP_REG_MERGE_CFG_12 0x040
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#define CFG_10_10_1PI_2PO_BUF_MODE 6
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#define CFG_10_10_2PI_2PO_BUF_MODE 8
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#define CFG_11_10_1PI_2PO_MERGE 18
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#define FLD_CFG_MERGE_MODE GENMASK(4, 0)
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#define DISP_REG_MERGE_CFG_24 0x070
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#define DISP_REG_MERGE_CFG_25 0x074
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#define DISP_REG_MERGE_CFG_26 0x078
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#define DISP_REG_MERGE_CFG_27 0x07c
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#define DISP_REG_MERGE_CFG_36 0x0a0
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#define ULTRA_EN BIT(0)
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#define PREULTRA_EN BIT(4)
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#define DISP_REG_MERGE_CFG_37 0x0a4
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/* 0: Off, 1: SRAM0, 2: SRAM1, 3: SRAM0 + SRAM1 */
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#define BUFFER_MODE 3
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#define FLD_BUFFER_MODE GENMASK(1, 0)
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/*
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* For the ultra and preultra settings, 6us ~ 9us is experience value
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* and the maximum frequency of mmsys clock is 594MHz.
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*/
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#define DISP_REG_MERGE_CFG_40 0x0b0
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/* 6 us, 594M pixel/sec */
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#define ULTRA_TH_LOW (6 * 594)
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/* 8 us, 594M pixel/sec */
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#define ULTRA_TH_HIGH (8 * 594)
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#define FLD_ULTRA_TH_LOW GENMASK(15, 0)
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#define FLD_ULTRA_TH_HIGH GENMASK(31, 16)
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#define DISP_REG_MERGE_CFG_41 0x0b4
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/* 8 us, 594M pixel/sec */
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#define PREULTRA_TH_LOW (8 * 594)
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/* 9 us, 594M pixel/sec */
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#define PREULTRA_TH_HIGH (9 * 594)
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#define FLD_PREULTRA_TH_LOW GENMASK(15, 0)
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#define FLD_PREULTRA_TH_HIGH GENMASK(31, 16)
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#define DISP_REG_MERGE_MUTE_0 0xf00
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struct mtk_disp_merge {
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void __iomem *regs;
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struct clk *clk;
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struct clk *async_clk;
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struct cmdq_client_reg cmdq_reg;
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bool fifo_en;
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bool mute_support;
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struct reset_control *reset_ctl;
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};
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void mtk_merge_start(struct device *dev)
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{
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mtk_merge_start_cmdq(dev, NULL);
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}
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void mtk_merge_stop(struct device *dev)
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{
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mtk_merge_stop_cmdq(dev, NULL);
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}
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void mtk_merge_start_cmdq(struct device *dev, struct cmdq_pkt *cmdq_pkt)
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{
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struct mtk_disp_merge *priv = dev_get_drvdata(dev);
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if (priv->mute_support)
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mtk_ddp_write(cmdq_pkt, 0x0, &priv->cmdq_reg, priv->regs,
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DISP_REG_MERGE_MUTE_0);
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mtk_ddp_write(cmdq_pkt, 1, &priv->cmdq_reg, priv->regs,
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DISP_REG_MERGE_CTRL);
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}
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void mtk_merge_stop_cmdq(struct device *dev, struct cmdq_pkt *cmdq_pkt)
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{
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struct mtk_disp_merge *priv = dev_get_drvdata(dev);
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if (priv->mute_support)
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mtk_ddp_write(cmdq_pkt, 0x1, &priv->cmdq_reg, priv->regs,
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DISP_REG_MERGE_MUTE_0);
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mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs,
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DISP_REG_MERGE_CTRL);
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if (priv->async_clk)
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reset_control_reset(priv->reset_ctl);
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}
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static void mtk_merge_fifo_setting(struct mtk_disp_merge *priv,
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struct cmdq_pkt *cmdq_pkt)
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{
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mtk_ddp_write(cmdq_pkt, ULTRA_EN | PREULTRA_EN,
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&priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_36);
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mtk_ddp_write_mask(cmdq_pkt, BUFFER_MODE,
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&priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_37,
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FLD_BUFFER_MODE);
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mtk_ddp_write_mask(cmdq_pkt, ULTRA_TH_LOW | ULTRA_TH_HIGH << 16,
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&priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_40,
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FLD_ULTRA_TH_LOW | FLD_ULTRA_TH_HIGH);
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mtk_ddp_write_mask(cmdq_pkt, PREULTRA_TH_LOW | PREULTRA_TH_HIGH << 16,
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&priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_41,
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FLD_PREULTRA_TH_LOW | FLD_PREULTRA_TH_HIGH);
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}
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void mtk_merge_config(struct device *dev, unsigned int w,
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unsigned int h, unsigned int vrefresh,
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unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
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{
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mtk_merge_advance_config(dev, w, 0, h, vrefresh, bpc, cmdq_pkt);
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}
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void mtk_merge_advance_config(struct device *dev, unsigned int l_w, unsigned int r_w,
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unsigned int h, unsigned int vrefresh, unsigned int bpc,
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struct cmdq_pkt *cmdq_pkt)
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{
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struct mtk_disp_merge *priv = dev_get_drvdata(dev);
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unsigned int mode = CFG_10_10_1PI_2PO_BUF_MODE;
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if (!h || !l_w) {
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dev_err(dev, "%s: input width(%d) or height(%d) is invalid\n", __func__, l_w, h);
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return;
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}
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if (priv->fifo_en) {
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mtk_merge_fifo_setting(priv, cmdq_pkt);
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mode = CFG_10_10_2PI_2PO_BUF_MODE;
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}
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if (r_w)
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mode = CFG_11_10_1PI_2PO_MERGE;
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mtk_ddp_write(cmdq_pkt, h << 16 | l_w, &priv->cmdq_reg, priv->regs,
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DISP_REG_MERGE_CFG_0);
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mtk_ddp_write(cmdq_pkt, h << 16 | r_w, &priv->cmdq_reg, priv->regs,
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DISP_REG_MERGE_CFG_1);
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mtk_ddp_write(cmdq_pkt, h << 16 | (l_w + r_w), &priv->cmdq_reg, priv->regs,
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DISP_REG_MERGE_CFG_4);
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/*
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* DISP_REG_MERGE_CFG_24 is merge SRAM0 w/h
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* DISP_REG_MERGE_CFG_25 is merge SRAM1 w/h.
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* If r_w > 0, the merge is in merge mode (input0 and input1 merge together),
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* the input0 goes to SRAM0, and input1 goes to SRAM1.
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* If r_w = 0, the merge is in buffer mode, the input goes through SRAM0 and
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* then to SRAM1. Both SRAM0 and SRAM1 are set to the same size.
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*/
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mtk_ddp_write(cmdq_pkt, h << 16 | l_w, &priv->cmdq_reg, priv->regs,
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DISP_REG_MERGE_CFG_24);
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if (r_w)
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mtk_ddp_write(cmdq_pkt, h << 16 | r_w, &priv->cmdq_reg, priv->regs,
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DISP_REG_MERGE_CFG_25);
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else
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mtk_ddp_write(cmdq_pkt, h << 16 | l_w, &priv->cmdq_reg, priv->regs,
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DISP_REG_MERGE_CFG_25);
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/*
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* DISP_REG_MERGE_CFG_26 and DISP_REG_MERGE_CFG_27 is only used in LR merge.
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* Only take effect when the merge is setting to merge mode.
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*/
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mtk_ddp_write(cmdq_pkt, h << 16 | l_w, &priv->cmdq_reg, priv->regs,
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DISP_REG_MERGE_CFG_26);
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mtk_ddp_write(cmdq_pkt, h << 16 | r_w, &priv->cmdq_reg, priv->regs,
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DISP_REG_MERGE_CFG_27);
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mtk_ddp_write_mask(cmdq_pkt, SWAP_MODE, &priv->cmdq_reg, priv->regs,
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DISP_REG_MERGE_CFG_10, FLD_SWAP_MODE);
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mtk_ddp_write_mask(cmdq_pkt, mode, &priv->cmdq_reg, priv->regs,
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DISP_REG_MERGE_CFG_12, FLD_CFG_MERGE_MODE);
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}
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int mtk_merge_clk_enable(struct device *dev)
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{
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int ret = 0;
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struct mtk_disp_merge *priv = dev_get_drvdata(dev);
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ret = clk_prepare_enable(priv->clk);
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if (ret) {
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dev_err(dev, "merge clk prepare enable failed\n");
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return ret;
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}
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ret = clk_prepare_enable(priv->async_clk);
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if (ret) {
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/* should clean up the state of priv->clk */
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clk_disable_unprepare(priv->clk);
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dev_err(dev, "async clk prepare enable failed\n");
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return ret;
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}
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return ret;
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}
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void mtk_merge_clk_disable(struct device *dev)
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{
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struct mtk_disp_merge *priv = dev_get_drvdata(dev);
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clk_disable_unprepare(priv->async_clk);
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clk_disable_unprepare(priv->clk);
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}
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static int mtk_disp_merge_bind(struct device *dev, struct device *master,
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void *data)
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{
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return 0;
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}
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static void mtk_disp_merge_unbind(struct device *dev, struct device *master,
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void *data)
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{
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}
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static const struct component_ops mtk_disp_merge_component_ops = {
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.bind = mtk_disp_merge_bind,
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.unbind = mtk_disp_merge_unbind,
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};
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static int mtk_disp_merge_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct resource *res;
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struct mtk_disp_merge *priv;
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int ret;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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priv->regs = devm_ioremap_resource(dev, res);
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if (IS_ERR(priv->regs)) {
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dev_err(dev, "failed to ioremap merge\n");
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return PTR_ERR(priv->regs);
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}
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priv->clk = devm_clk_get(dev, NULL);
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if (IS_ERR(priv->clk)) {
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dev_err(dev, "failed to get merge clk\n");
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return PTR_ERR(priv->clk);
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}
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priv->async_clk = devm_clk_get_optional(dev, "merge_async");
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if (IS_ERR(priv->async_clk)) {
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dev_err(dev, "failed to get merge async clock\n");
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return PTR_ERR(priv->async_clk);
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}
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if (priv->async_clk) {
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priv->reset_ctl = devm_reset_control_get_optional_exclusive(dev, NULL);
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if (IS_ERR(priv->reset_ctl))
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return PTR_ERR(priv->reset_ctl);
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}
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#if IS_REACHABLE(CONFIG_MTK_CMDQ)
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ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);
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if (ret)
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dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
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#endif
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priv->fifo_en = of_property_read_bool(dev->of_node,
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"mediatek,merge-fifo-en");
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priv->mute_support = of_property_read_bool(dev->of_node,
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"mediatek,merge-mute");
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platform_set_drvdata(pdev, priv);
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ret = component_add(dev, &mtk_disp_merge_component_ops);
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if (ret != 0)
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dev_err(dev, "Failed to add component: %d\n", ret);
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return ret;
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}
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static int mtk_disp_merge_remove(struct platform_device *pdev)
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{
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component_del(&pdev->dev, &mtk_disp_merge_component_ops);
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return 0;
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}
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static const struct of_device_id mtk_disp_merge_driver_dt_match[] = {
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{ .compatible = "mediatek,mt8195-disp-merge", },
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{},
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};
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MODULE_DEVICE_TABLE(of, mtk_disp_merge_driver_dt_match);
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struct platform_driver mtk_disp_merge_driver = {
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.probe = mtk_disp_merge_probe,
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.remove = mtk_disp_merge_remove,
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.driver = {
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.name = "mediatek-disp-merge",
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.owner = THIS_MODULE,
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.of_match_table = mtk_disp_merge_driver_dt_match,
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},
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};
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