126 lines
2.6 KiB
C
126 lines
2.6 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
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*/
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#include "dpu_hwio.h"
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#include "dpu_hw_catalog.h"
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#include "dpu_hw_lm.h"
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#include "dpu_hw_dspp.h"
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#include "dpu_kms.h"
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/* DSPP_PCC */
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#define PCC_EN BIT(0)
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#define PCC_DIS 0
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#define PCC_RED_R_OFF 0x10
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#define PCC_RED_G_OFF 0x1C
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#define PCC_RED_B_OFF 0x28
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#define PCC_GREEN_R_OFF 0x14
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#define PCC_GREEN_G_OFF 0x20
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#define PCC_GREEN_B_OFF 0x2C
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#define PCC_BLUE_R_OFF 0x18
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#define PCC_BLUE_G_OFF 0x24
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#define PCC_BLUE_B_OFF 0x30
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static void dpu_setup_dspp_pcc(struct dpu_hw_dspp *ctx,
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struct dpu_hw_pcc_cfg *cfg)
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{
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u32 base;
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if (!ctx) {
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DRM_ERROR("invalid ctx %pK\n", ctx);
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return;
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}
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base = ctx->cap->sblk->pcc.base;
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if (!base) {
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DRM_ERROR("invalid ctx %pK pcc base 0x%x\n", ctx, base);
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return;
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}
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if (!cfg) {
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DRM_DEBUG_DRIVER("disable pcc feature\n");
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DPU_REG_WRITE(&ctx->hw, base, PCC_DIS);
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return;
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}
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DPU_REG_WRITE(&ctx->hw, base + PCC_RED_R_OFF, cfg->r.r);
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DPU_REG_WRITE(&ctx->hw, base + PCC_RED_G_OFF, cfg->r.g);
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DPU_REG_WRITE(&ctx->hw, base + PCC_RED_B_OFF, cfg->r.b);
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DPU_REG_WRITE(&ctx->hw, base + PCC_GREEN_R_OFF, cfg->g.r);
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DPU_REG_WRITE(&ctx->hw, base + PCC_GREEN_G_OFF, cfg->g.g);
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DPU_REG_WRITE(&ctx->hw, base + PCC_GREEN_B_OFF, cfg->g.b);
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DPU_REG_WRITE(&ctx->hw, base + PCC_BLUE_R_OFF, cfg->b.r);
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DPU_REG_WRITE(&ctx->hw, base + PCC_BLUE_G_OFF, cfg->b.g);
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DPU_REG_WRITE(&ctx->hw, base + PCC_BLUE_B_OFF, cfg->b.b);
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DPU_REG_WRITE(&ctx->hw, base, PCC_EN);
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}
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static void _setup_dspp_ops(struct dpu_hw_dspp *c,
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unsigned long features)
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{
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if (test_bit(DPU_DSPP_PCC, &features))
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c->ops.setup_pcc = dpu_setup_dspp_pcc;
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}
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static const struct dpu_dspp_cfg *_dspp_offset(enum dpu_dspp dspp,
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const struct dpu_mdss_cfg *m,
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void __iomem *addr,
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struct dpu_hw_blk_reg_map *b)
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{
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int i;
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if (!m || !addr || !b)
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return ERR_PTR(-EINVAL);
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for (i = 0; i < m->dspp_count; i++) {
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if (dspp == m->dspp[i].id) {
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b->blk_addr = addr + m->dspp[i].base;
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b->log_mask = DPU_DBG_MASK_DSPP;
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return &m->dspp[i];
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}
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}
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return ERR_PTR(-EINVAL);
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}
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struct dpu_hw_dspp *dpu_hw_dspp_init(enum dpu_dspp idx,
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void __iomem *addr,
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const struct dpu_mdss_cfg *m)
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{
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struct dpu_hw_dspp *c;
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const struct dpu_dspp_cfg *cfg;
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if (!addr || !m)
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return ERR_PTR(-EINVAL);
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c = kzalloc(sizeof(*c), GFP_KERNEL);
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if (!c)
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return ERR_PTR(-ENOMEM);
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cfg = _dspp_offset(idx, m, addr, &c->hw);
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if (IS_ERR_OR_NULL(cfg)) {
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kfree(c);
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return ERR_PTR(-EINVAL);
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}
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/* Assign ops */
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c->idx = idx;
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c->cap = cfg;
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_setup_dspp_ops(c, c->cap->features);
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return c;
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}
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void dpu_hw_dspp_destroy(struct dpu_hw_dspp *dspp)
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{
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kfree(dspp);
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}
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