220 lines
5.9 KiB
C
220 lines
5.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2013 Red Hat
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* Author: Rob Clark <robdclark@gmail.com>
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*/
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#ifndef __MDP4_KMS_H__
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#define __MDP4_KMS_H__
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#include <drm/drm_panel.h>
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#include "msm_drv.h"
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#include "msm_kms.h"
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#include "disp/mdp_kms.h"
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#include "mdp4.xml.h"
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struct device_node;
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struct mdp4_kms {
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struct mdp_kms base;
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struct drm_device *dev;
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int rev;
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void __iomem *mmio;
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struct regulator *vdd;
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struct clk *clk;
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struct clk *pclk;
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struct clk *lut_clk;
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struct clk *axi_clk;
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struct mdp_irq error_handler;
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bool rpm_enabled;
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/* empty/blank cursor bo to use when cursor is "disabled" */
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struct drm_gem_object *blank_cursor_bo;
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uint64_t blank_cursor_iova;
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};
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#define to_mdp4_kms(x) container_of(x, struct mdp4_kms, base)
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static inline void mdp4_write(struct mdp4_kms *mdp4_kms, u32 reg, u32 data)
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{
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msm_writel(data, mdp4_kms->mmio + reg);
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}
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static inline u32 mdp4_read(struct mdp4_kms *mdp4_kms, u32 reg)
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{
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return msm_readl(mdp4_kms->mmio + reg);
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}
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static inline uint32_t pipe2flush(enum mdp4_pipe pipe)
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{
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switch (pipe) {
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case VG1: return MDP4_OVERLAY_FLUSH_VG1;
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case VG2: return MDP4_OVERLAY_FLUSH_VG2;
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case RGB1: return MDP4_OVERLAY_FLUSH_RGB1;
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case RGB2: return MDP4_OVERLAY_FLUSH_RGB2;
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default: return 0;
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}
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}
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static inline uint32_t ovlp2flush(int ovlp)
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{
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switch (ovlp) {
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case 0: return MDP4_OVERLAY_FLUSH_OVLP0;
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case 1: return MDP4_OVERLAY_FLUSH_OVLP1;
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default: return 0;
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}
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}
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static inline uint32_t dma2irq(enum mdp4_dma dma)
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{
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switch (dma) {
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case DMA_P: return MDP4_IRQ_DMA_P_DONE;
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case DMA_S: return MDP4_IRQ_DMA_S_DONE;
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case DMA_E: return MDP4_IRQ_DMA_E_DONE;
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default: return 0;
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}
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}
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static inline uint32_t dma2err(enum mdp4_dma dma)
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{
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switch (dma) {
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case DMA_P: return MDP4_IRQ_PRIMARY_INTF_UDERRUN;
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case DMA_S: return 0; // ???
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case DMA_E: return MDP4_IRQ_EXTERNAL_INTF_UDERRUN;
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default: return 0;
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}
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}
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static inline uint32_t mixercfg(uint32_t mixer_cfg, int mixer,
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enum mdp4_pipe pipe, enum mdp_mixer_stage_id stage)
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{
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switch (pipe) {
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case VG1:
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mixer_cfg &= ~(MDP4_LAYERMIXER_IN_CFG_PIPE0__MASK |
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MDP4_LAYERMIXER_IN_CFG_PIPE0_MIXER1);
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mixer_cfg |= MDP4_LAYERMIXER_IN_CFG_PIPE0(stage) |
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COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE0_MIXER1);
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break;
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case VG2:
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mixer_cfg &= ~(MDP4_LAYERMIXER_IN_CFG_PIPE1__MASK |
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MDP4_LAYERMIXER_IN_CFG_PIPE1_MIXER1);
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mixer_cfg |= MDP4_LAYERMIXER_IN_CFG_PIPE1(stage) |
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COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE1_MIXER1);
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break;
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case RGB1:
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mixer_cfg &= ~(MDP4_LAYERMIXER_IN_CFG_PIPE2__MASK |
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MDP4_LAYERMIXER_IN_CFG_PIPE2_MIXER1);
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mixer_cfg |= MDP4_LAYERMIXER_IN_CFG_PIPE2(stage) |
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COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE2_MIXER1);
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break;
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case RGB2:
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mixer_cfg &= ~(MDP4_LAYERMIXER_IN_CFG_PIPE3__MASK |
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MDP4_LAYERMIXER_IN_CFG_PIPE3_MIXER1);
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mixer_cfg |= MDP4_LAYERMIXER_IN_CFG_PIPE3(stage) |
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COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE3_MIXER1);
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break;
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case RGB3:
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mixer_cfg &= ~(MDP4_LAYERMIXER_IN_CFG_PIPE4__MASK |
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MDP4_LAYERMIXER_IN_CFG_PIPE4_MIXER1);
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mixer_cfg |= MDP4_LAYERMIXER_IN_CFG_PIPE4(stage) |
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COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE4_MIXER1);
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break;
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case VG3:
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mixer_cfg &= ~(MDP4_LAYERMIXER_IN_CFG_PIPE5__MASK |
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MDP4_LAYERMIXER_IN_CFG_PIPE5_MIXER1);
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mixer_cfg |= MDP4_LAYERMIXER_IN_CFG_PIPE5(stage) |
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COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE5_MIXER1);
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break;
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case VG4:
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mixer_cfg &= ~(MDP4_LAYERMIXER_IN_CFG_PIPE6__MASK |
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MDP4_LAYERMIXER_IN_CFG_PIPE6_MIXER1);
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mixer_cfg |= MDP4_LAYERMIXER_IN_CFG_PIPE6(stage) |
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COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE6_MIXER1);
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break;
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default:
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WARN(1, "invalid pipe");
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break;
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}
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return mixer_cfg;
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}
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int mdp4_disable(struct mdp4_kms *mdp4_kms);
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int mdp4_enable(struct mdp4_kms *mdp4_kms);
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void mdp4_set_irqmask(struct mdp_kms *mdp_kms, uint32_t irqmask,
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uint32_t old_irqmask);
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void mdp4_irq_preinstall(struct msm_kms *kms);
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int mdp4_irq_postinstall(struct msm_kms *kms);
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void mdp4_irq_uninstall(struct msm_kms *kms);
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irqreturn_t mdp4_irq(struct msm_kms *kms);
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int mdp4_enable_vblank(struct msm_kms *kms, struct drm_crtc *crtc);
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void mdp4_disable_vblank(struct msm_kms *kms, struct drm_crtc *crtc);
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static inline uint32_t mdp4_pipe_caps(enum mdp4_pipe pipe)
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{
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switch (pipe) {
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case VG1:
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case VG2:
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case VG3:
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case VG4:
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return MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
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MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC;
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case RGB1:
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case RGB2:
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case RGB3:
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return MDP_PIPE_CAP_SCALE;
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default:
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return 0;
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}
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}
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enum mdp4_pipe mdp4_plane_pipe(struct drm_plane *plane);
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struct drm_plane *mdp4_plane_init(struct drm_device *dev,
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enum mdp4_pipe pipe_id, bool private_plane);
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uint32_t mdp4_crtc_vblank(struct drm_crtc *crtc);
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void mdp4_crtc_set_config(struct drm_crtc *crtc, uint32_t config);
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void mdp4_crtc_set_intf(struct drm_crtc *crtc, enum mdp4_intf intf, int mixer);
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void mdp4_crtc_wait_for_commit_done(struct drm_crtc *crtc);
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struct drm_crtc *mdp4_crtc_init(struct drm_device *dev,
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struct drm_plane *plane, int id, int ovlp_id,
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enum mdp4_dma dma_id);
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long mdp4_dtv_round_pixclk(struct drm_encoder *encoder, unsigned long rate);
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struct drm_encoder *mdp4_dtv_encoder_init(struct drm_device *dev);
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long mdp4_lcdc_round_pixclk(struct drm_encoder *encoder, unsigned long rate);
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struct drm_encoder *mdp4_lcdc_encoder_init(struct drm_device *dev,
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struct device_node *panel_node);
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struct drm_connector *mdp4_lvds_connector_init(struct drm_device *dev,
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struct device_node *panel_node, struct drm_encoder *encoder);
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#ifdef CONFIG_DRM_MSM_DSI
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struct drm_encoder *mdp4_dsi_encoder_init(struct drm_device *dev);
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#else
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static inline struct drm_encoder *mdp4_dsi_encoder_init(struct drm_device *dev)
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{
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return ERR_PTR(-ENODEV);
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}
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#endif
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#ifdef CONFIG_COMMON_CLK
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struct clk *mpd4_lvds_pll_init(struct drm_device *dev);
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#else
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static inline struct clk *mpd4_lvds_pll_init(struct drm_device *dev)
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{
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return ERR_PTR(-ENODEV);
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}
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#endif
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#endif /* __MDP4_KMS_H__ */
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