560 lines
13 KiB
C
560 lines
13 KiB
C
/*
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* SPDX-License-Identifier: GPL-2.0
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* Copyright (c) 2018, The Linux Foundation
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/interconnect.h>
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#include <linux/irq.h>
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#include <linux/irqchip.h>
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#include <linux/irqdesc.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/pm_runtime.h>
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#include <linux/reset.h>
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#include "msm_drv.h"
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#include "msm_kms.h"
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/* for DPU_HW_* defines */
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#include "disp/dpu1/dpu_hw_catalog.h"
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#define HW_REV 0x0
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#define HW_INTR_STATUS 0x0010
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#define UBWC_DEC_HW_VERSION 0x58
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#define UBWC_STATIC 0x144
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#define UBWC_CTRL_2 0x150
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#define UBWC_PREDICTION_MODE 0x154
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#define MIN_IB_BW 400000000UL /* Min ib vote 400MB */
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struct msm_mdss {
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struct device *dev;
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void __iomem *mmio;
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struct clk_bulk_data *clocks;
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size_t num_clocks;
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bool is_mdp5;
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struct {
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unsigned long enabled_mask;
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struct irq_domain *domain;
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} irq_controller;
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struct icc_path *path[2];
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u32 num_paths;
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};
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static int msm_mdss_parse_data_bus_icc_path(struct device *dev,
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struct msm_mdss *msm_mdss)
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{
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struct icc_path *path0;
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struct icc_path *path1;
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path0 = of_icc_get(dev, "mdp0-mem");
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if (IS_ERR_OR_NULL(path0))
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return PTR_ERR_OR_ZERO(path0);
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msm_mdss->path[0] = path0;
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msm_mdss->num_paths = 1;
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path1 = of_icc_get(dev, "mdp1-mem");
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if (!IS_ERR_OR_NULL(path1)) {
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msm_mdss->path[1] = path1;
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msm_mdss->num_paths++;
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}
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return 0;
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}
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static void msm_mdss_put_icc_path(void *data)
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{
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struct msm_mdss *msm_mdss = data;
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int i;
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for (i = 0; i < msm_mdss->num_paths; i++)
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icc_put(msm_mdss->path[i]);
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}
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static void msm_mdss_icc_request_bw(struct msm_mdss *msm_mdss, unsigned long bw)
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{
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int i;
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for (i = 0; i < msm_mdss->num_paths; i++)
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icc_set_bw(msm_mdss->path[i], 0, Bps_to_icc(bw));
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}
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static void msm_mdss_irq(struct irq_desc *desc)
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{
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struct msm_mdss *msm_mdss = irq_desc_get_handler_data(desc);
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struct irq_chip *chip = irq_desc_get_chip(desc);
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u32 interrupts;
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chained_irq_enter(chip, desc);
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interrupts = readl_relaxed(msm_mdss->mmio + HW_INTR_STATUS);
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while (interrupts) {
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irq_hw_number_t hwirq = fls(interrupts) - 1;
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int rc;
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rc = generic_handle_domain_irq(msm_mdss->irq_controller.domain,
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hwirq);
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if (rc < 0) {
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dev_err(msm_mdss->dev, "handle irq fail: irq=%lu rc=%d\n",
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hwirq, rc);
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break;
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}
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interrupts &= ~(1 << hwirq);
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}
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chained_irq_exit(chip, desc);
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}
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static void msm_mdss_irq_mask(struct irq_data *irqd)
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{
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struct msm_mdss *msm_mdss = irq_data_get_irq_chip_data(irqd);
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/* memory barrier */
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smp_mb__before_atomic();
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clear_bit(irqd->hwirq, &msm_mdss->irq_controller.enabled_mask);
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/* memory barrier */
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smp_mb__after_atomic();
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}
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static void msm_mdss_irq_unmask(struct irq_data *irqd)
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{
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struct msm_mdss *msm_mdss = irq_data_get_irq_chip_data(irqd);
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/* memory barrier */
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smp_mb__before_atomic();
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set_bit(irqd->hwirq, &msm_mdss->irq_controller.enabled_mask);
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/* memory barrier */
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smp_mb__after_atomic();
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}
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static struct irq_chip msm_mdss_irq_chip = {
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.name = "msm_mdss",
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.irq_mask = msm_mdss_irq_mask,
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.irq_unmask = msm_mdss_irq_unmask,
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};
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static struct lock_class_key msm_mdss_lock_key, msm_mdss_request_key;
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static int msm_mdss_irqdomain_map(struct irq_domain *domain,
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unsigned int irq, irq_hw_number_t hwirq)
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{
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struct msm_mdss *msm_mdss = domain->host_data;
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irq_set_lockdep_class(irq, &msm_mdss_lock_key, &msm_mdss_request_key);
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irq_set_chip_and_handler(irq, &msm_mdss_irq_chip, handle_level_irq);
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return irq_set_chip_data(irq, msm_mdss);
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}
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static const struct irq_domain_ops msm_mdss_irqdomain_ops = {
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.map = msm_mdss_irqdomain_map,
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.xlate = irq_domain_xlate_onecell,
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};
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static int _msm_mdss_irq_domain_add(struct msm_mdss *msm_mdss)
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{
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struct device *dev;
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struct irq_domain *domain;
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dev = msm_mdss->dev;
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domain = irq_domain_add_linear(dev->of_node, 32,
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&msm_mdss_irqdomain_ops, msm_mdss);
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if (!domain) {
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dev_err(dev, "failed to add irq_domain\n");
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return -EINVAL;
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}
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msm_mdss->irq_controller.enabled_mask = 0;
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msm_mdss->irq_controller.domain = domain;
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return 0;
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}
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#define UBWC_1_0 0x10000000
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#define UBWC_2_0 0x20000000
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#define UBWC_3_0 0x30000000
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#define UBWC_4_0 0x40000000
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static void msm_mdss_setup_ubwc_dec_20(struct msm_mdss *msm_mdss,
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u32 ubwc_static)
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{
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writel_relaxed(ubwc_static, msm_mdss->mmio + UBWC_STATIC);
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}
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static void msm_mdss_setup_ubwc_dec_30(struct msm_mdss *msm_mdss,
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unsigned int ubwc_version,
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u32 ubwc_swizzle,
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u32 highest_bank_bit,
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u32 macrotile_mode)
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{
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u32 value = (ubwc_swizzle & 0x1) |
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(highest_bank_bit & 0x3) << 4 |
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(macrotile_mode & 0x1) << 12;
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if (ubwc_version == UBWC_3_0)
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value |= BIT(10);
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if (ubwc_version == UBWC_1_0)
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value |= BIT(8);
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writel_relaxed(value, msm_mdss->mmio + UBWC_STATIC);
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}
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static void msm_mdss_setup_ubwc_dec_40(struct msm_mdss *msm_mdss,
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unsigned int ubwc_version,
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u32 ubwc_swizzle,
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u32 ubwc_static,
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u32 highest_bank_bit,
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u32 macrotile_mode)
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{
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u32 value = (ubwc_swizzle & 0x7) |
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(ubwc_static & 0x1) << 3 |
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(highest_bank_bit & 0x7) << 4 |
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(macrotile_mode & 0x1) << 12;
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writel_relaxed(value, msm_mdss->mmio + UBWC_STATIC);
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if (ubwc_version == UBWC_3_0) {
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writel_relaxed(1, msm_mdss->mmio + UBWC_CTRL_2);
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writel_relaxed(0, msm_mdss->mmio + UBWC_PREDICTION_MODE);
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} else {
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writel_relaxed(2, msm_mdss->mmio + UBWC_CTRL_2);
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writel_relaxed(1, msm_mdss->mmio + UBWC_PREDICTION_MODE);
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}
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}
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static int msm_mdss_enable(struct msm_mdss *msm_mdss)
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{
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int ret;
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u32 hw_rev;
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/*
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* Several components have AXI clocks that can only be turned on if
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* the interconnect is enabled (non-zero bandwidth). Let's make sure
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* that the interconnects are at least at a minimum amount.
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*/
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msm_mdss_icc_request_bw(msm_mdss, MIN_IB_BW);
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ret = clk_bulk_prepare_enable(msm_mdss->num_clocks, msm_mdss->clocks);
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if (ret) {
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dev_err(msm_mdss->dev, "clock enable failed, ret:%d\n", ret);
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return ret;
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}
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/*
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* HW_REV requires MDSS_MDP_CLK, which is not enabled by the mdss on
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* mdp5 hardware. Skip reading it for now.
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*/
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if (msm_mdss->is_mdp5)
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return 0;
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hw_rev = readl_relaxed(msm_mdss->mmio + HW_REV);
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dev_dbg(msm_mdss->dev, "HW_REV: 0x%x\n", hw_rev);
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dev_dbg(msm_mdss->dev, "UBWC_DEC_HW_VERSION: 0x%x\n",
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readl_relaxed(msm_mdss->mmio + UBWC_DEC_HW_VERSION));
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/*
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* ubwc config is part of the "mdss" region which is not accessible
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* from the rest of the driver. hardcode known configurations here
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*
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* Decoder version can be read from the UBWC_DEC_HW_VERSION reg,
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* UBWC_n and the rest of params comes from hw_catalog.
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* Unforunately this driver can not access hw catalog, so we have to
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* hardcode them here.
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*/
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switch (hw_rev) {
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case DPU_HW_VER_500:
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case DPU_HW_VER_501:
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msm_mdss_setup_ubwc_dec_30(msm_mdss, UBWC_3_0, 0, 2, 0);
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break;
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case DPU_HW_VER_600:
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/* TODO: highest_bank_bit = 2 for LP_DDR4 */
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msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_4_0, 6, 1, 3, 1);
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break;
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case DPU_HW_VER_620:
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/* UBWC_2_0 */
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msm_mdss_setup_ubwc_dec_20(msm_mdss, 0x1e);
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break;
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case DPU_HW_VER_630:
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/* UBWC_2_0 */
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msm_mdss_setup_ubwc_dec_20(msm_mdss, 0x11f);
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break;
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case DPU_HW_VER_700:
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/* TODO: highest_bank_bit = 2 for LP_DDR4 */
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msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_4_0, 6, 1, 3, 1);
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break;
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case DPU_HW_VER_720:
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msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_3_0, 6, 1, 1, 1);
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break;
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case DPU_HW_VER_800:
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msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_4_0, 6, 1, 2, 1);
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break;
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case DPU_HW_VER_810:
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case DPU_HW_VER_900:
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/* TODO: highest_bank_bit = 2 for LP_DDR4 */
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msm_mdss_setup_ubwc_dec_40(msm_mdss, UBWC_4_0, 6, 1, 3, 1);
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break;
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}
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return ret;
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}
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static int msm_mdss_disable(struct msm_mdss *msm_mdss)
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{
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clk_bulk_disable_unprepare(msm_mdss->num_clocks, msm_mdss->clocks);
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msm_mdss_icc_request_bw(msm_mdss, 0);
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return 0;
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}
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static void msm_mdss_destroy(struct msm_mdss *msm_mdss)
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{
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struct platform_device *pdev = to_platform_device(msm_mdss->dev);
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int irq;
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pm_runtime_suspend(msm_mdss->dev);
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pm_runtime_disable(msm_mdss->dev);
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irq_domain_remove(msm_mdss->irq_controller.domain);
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msm_mdss->irq_controller.domain = NULL;
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irq = platform_get_irq(pdev, 0);
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irq_set_chained_handler_and_data(irq, NULL, NULL);
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}
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static int msm_mdss_reset(struct device *dev)
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{
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struct reset_control *reset;
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reset = reset_control_get_optional_exclusive(dev, NULL);
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if (!reset) {
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/* Optional reset not specified */
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return 0;
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} else if (IS_ERR(reset)) {
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return dev_err_probe(dev, PTR_ERR(reset),
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"failed to acquire mdss reset\n");
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}
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reset_control_assert(reset);
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/*
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* Tests indicate that reset has to be held for some period of time,
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* make it one frame in a typical system
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*/
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msleep(20);
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reset_control_deassert(reset);
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reset_control_put(reset);
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return 0;
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}
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/*
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* MDP5 MDSS uses at most three specified clocks.
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*/
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#define MDP5_MDSS_NUM_CLOCKS 3
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static int mdp5_mdss_parse_clock(struct platform_device *pdev, struct clk_bulk_data **clocks)
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{
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struct clk_bulk_data *bulk;
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int num_clocks = 0;
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int ret;
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if (!pdev)
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return -EINVAL;
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bulk = devm_kcalloc(&pdev->dev, MDP5_MDSS_NUM_CLOCKS, sizeof(struct clk_bulk_data), GFP_KERNEL);
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if (!bulk)
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return -ENOMEM;
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bulk[num_clocks++].id = "iface";
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bulk[num_clocks++].id = "bus";
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bulk[num_clocks++].id = "vsync";
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ret = devm_clk_bulk_get_optional(&pdev->dev, num_clocks, bulk);
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if (ret)
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return ret;
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*clocks = bulk;
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return num_clocks;
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}
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static struct msm_mdss *msm_mdss_init(struct platform_device *pdev, bool is_mdp5)
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{
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struct msm_mdss *msm_mdss;
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int ret;
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int irq;
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ret = msm_mdss_reset(&pdev->dev);
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if (ret)
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return ERR_PTR(ret);
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msm_mdss = devm_kzalloc(&pdev->dev, sizeof(*msm_mdss), GFP_KERNEL);
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if (!msm_mdss)
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return ERR_PTR(-ENOMEM);
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msm_mdss->mmio = devm_platform_ioremap_resource_byname(pdev, is_mdp5 ? "mdss_phys" : "mdss");
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if (IS_ERR(msm_mdss->mmio))
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return ERR_CAST(msm_mdss->mmio);
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dev_dbg(&pdev->dev, "mapped mdss address space @%pK\n", msm_mdss->mmio);
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ret = msm_mdss_parse_data_bus_icc_path(&pdev->dev, msm_mdss);
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if (ret)
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return ERR_PTR(ret);
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ret = devm_add_action_or_reset(&pdev->dev, msm_mdss_put_icc_path, msm_mdss);
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if (ret)
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return ERR_PTR(ret);
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if (is_mdp5)
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ret = mdp5_mdss_parse_clock(pdev, &msm_mdss->clocks);
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else
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ret = devm_clk_bulk_get_all(&pdev->dev, &msm_mdss->clocks);
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if (ret < 0) {
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dev_err(&pdev->dev, "failed to parse clocks, ret=%d\n", ret);
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return ERR_PTR(ret);
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}
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msm_mdss->num_clocks = ret;
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msm_mdss->is_mdp5 = is_mdp5;
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msm_mdss->dev = &pdev->dev;
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irq = platform_get_irq(pdev, 0);
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if (irq < 0)
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return ERR_PTR(irq);
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ret = _msm_mdss_irq_domain_add(msm_mdss);
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if (ret)
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return ERR_PTR(ret);
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irq_set_chained_handler_and_data(irq, msm_mdss_irq,
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msm_mdss);
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pm_runtime_enable(&pdev->dev);
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return msm_mdss;
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}
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static int __maybe_unused mdss_runtime_suspend(struct device *dev)
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{
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struct msm_mdss *mdss = dev_get_drvdata(dev);
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DBG("");
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return msm_mdss_disable(mdss);
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}
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static int __maybe_unused mdss_runtime_resume(struct device *dev)
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{
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struct msm_mdss *mdss = dev_get_drvdata(dev);
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DBG("");
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return msm_mdss_enable(mdss);
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}
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static int __maybe_unused mdss_pm_suspend(struct device *dev)
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{
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if (pm_runtime_suspended(dev))
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return 0;
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return mdss_runtime_suspend(dev);
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}
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static int __maybe_unused mdss_pm_resume(struct device *dev)
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{
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if (pm_runtime_suspended(dev))
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return 0;
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return mdss_runtime_resume(dev);
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}
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static const struct dev_pm_ops mdss_pm_ops = {
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SET_SYSTEM_SLEEP_PM_OPS(mdss_pm_suspend, mdss_pm_resume)
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SET_RUNTIME_PM_OPS(mdss_runtime_suspend, mdss_runtime_resume, NULL)
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};
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static int mdss_probe(struct platform_device *pdev)
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{
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struct msm_mdss *mdss;
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bool is_mdp5 = of_device_is_compatible(pdev->dev.of_node, "qcom,mdss");
|
|
struct device *dev = &pdev->dev;
|
|
int ret;
|
|
|
|
mdss = msm_mdss_init(pdev, is_mdp5);
|
|
if (IS_ERR(mdss))
|
|
return PTR_ERR(mdss);
|
|
|
|
platform_set_drvdata(pdev, mdss);
|
|
|
|
/*
|
|
* MDP5/DPU based devices don't have a flat hierarchy. There is a top
|
|
* level parent: MDSS, and children: MDP5/DPU, DSI, HDMI, eDP etc.
|
|
* Populate the children devices, find the MDP5/DPU node, and then add
|
|
* the interfaces to our components list.
|
|
*/
|
|
ret = of_platform_populate(dev->of_node, NULL, NULL, dev);
|
|
if (ret) {
|
|
DRM_DEV_ERROR(dev, "failed to populate children devices\n");
|
|
msm_mdss_destroy(mdss);
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int mdss_remove(struct platform_device *pdev)
|
|
{
|
|
struct msm_mdss *mdss = platform_get_drvdata(pdev);
|
|
|
|
of_platform_depopulate(&pdev->dev);
|
|
|
|
msm_mdss_destroy(mdss);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct of_device_id mdss_dt_match[] = {
|
|
{ .compatible = "qcom,mdss" },
|
|
{ .compatible = "qcom,msm8998-mdss" },
|
|
{ .compatible = "qcom,qcm2290-mdss" },
|
|
{ .compatible = "qcom,sdm845-mdss" },
|
|
{ .compatible = "qcom,sc7180-mdss" },
|
|
{ .compatible = "qcom,sc7280-mdss" },
|
|
{ .compatible = "qcom,sc8180x-mdss" },
|
|
{ .compatible = "qcom,sc8280xp-mdss" },
|
|
{ .compatible = "qcom,sm6115-mdss" },
|
|
{ .compatible = "qcom,sm8150-mdss" },
|
|
{ .compatible = "qcom,sm8250-mdss" },
|
|
{ .compatible = "qcom,sm8350-mdss" },
|
|
{ .compatible = "qcom,sm8450-mdss" },
|
|
{ .compatible = "qcom,sm8550-mdss" },
|
|
{}
|
|
};
|
|
MODULE_DEVICE_TABLE(of, mdss_dt_match);
|
|
|
|
static struct platform_driver mdss_platform_driver = {
|
|
.probe = mdss_probe,
|
|
.remove = mdss_remove,
|
|
.driver = {
|
|
.name = "msm-mdss",
|
|
.of_match_table = mdss_dt_match,
|
|
.pm = &mdss_pm_ops,
|
|
},
|
|
};
|
|
|
|
void __init msm_mdss_register(void)
|
|
{
|
|
platform_driver_register(&mdss_platform_driver);
|
|
}
|
|
|
|
void __exit msm_mdss_unregister(void)
|
|
{
|
|
platform_driver_unregister(&mdss_platform_driver);
|
|
}
|