188 lines
5.6 KiB
C
188 lines
5.6 KiB
C
/*
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* Copyright 2012 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include "priv.h"
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#include "chan.h"
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#include "hdmi.h"
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#include "head.h"
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#include "ior.h"
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#include "outp.h"
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#include <nvif/class.h>
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void
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gm200_sor_dp_drive(struct nvkm_ior *sor, int ln, int pc, int dc, int pe, int pu)
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{
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struct nvkm_device *device = sor->disp->engine.subdev.device;
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const u32 loff = nv50_sor_link(sor);
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const u32 shift = sor->func->dp->lanes[ln] * 8;
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u32 data[4];
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pu &= 0x0f;
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data[0] = nvkm_rd32(device, 0x61c118 + loff) & ~(0x000000ff << shift);
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data[1] = nvkm_rd32(device, 0x61c120 + loff) & ~(0x000000ff << shift);
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data[2] = nvkm_rd32(device, 0x61c130 + loff);
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if ((data[2] & 0x00000f00) < (pu << 8) || ln == 0)
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data[2] = (data[2] & ~0x00000f00) | (pu << 8);
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nvkm_wr32(device, 0x61c118 + loff, data[0] | (dc << shift));
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nvkm_wr32(device, 0x61c120 + loff, data[1] | (pe << shift));
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nvkm_wr32(device, 0x61c130 + loff, data[2]);
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data[3] = nvkm_rd32(device, 0x61c13c + loff) & ~(0x000000ff << shift);
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nvkm_wr32(device, 0x61c13c + loff, data[3] | (pc << shift));
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}
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const struct nvkm_ior_func_dp
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gm200_sor_dp = {
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.lanes = { 0, 1, 2, 3 },
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.links = gf119_sor_dp_links,
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.power = g94_sor_dp_power,
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.pattern = gm107_sor_dp_pattern,
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.drive = gm200_sor_dp_drive,
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.vcpi = gf119_sor_dp_vcpi,
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.audio = gf119_sor_dp_audio,
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.audio_sym = gf119_sor_dp_audio_sym,
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.watermark = gf119_sor_dp_watermark,
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};
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void
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gm200_sor_hdmi_scdc(struct nvkm_ior *ior, u8 scdc)
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{
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struct nvkm_device *device = ior->disp->engine.subdev.device;
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const u32 soff = nv50_ior_base(ior);
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const u32 ctrl = scdc & 0x3;
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nvkm_mask(device, 0x61c5bc + soff, 0x00000003, ctrl);
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ior->tmds.high_speed = !!(scdc & 0x2);
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}
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const struct nvkm_ior_func_hdmi
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gm200_sor_hdmi = {
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.ctrl = gk104_sor_hdmi_ctrl,
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.scdc = gm200_sor_hdmi_scdc,
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.infoframe_avi = gk104_sor_hdmi_infoframe_avi,
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.infoframe_vsi = gk104_sor_hdmi_infoframe_vsi,
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};
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void
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gm200_sor_route_set(struct nvkm_outp *outp, struct nvkm_ior *ior)
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{
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struct nvkm_device *device = outp->disp->engine.subdev.device;
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const u32 moff = __ffs(outp->info.or) * 0x100;
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const u32 sor = ior ? ior->id + 1 : 0;
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u32 link = ior ? (ior->asy.link == 2) : 0;
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if (outp->info.sorconf.link & 1) {
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nvkm_mask(device, 0x612308 + moff, 0x0000001f, link << 4 | sor);
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link++;
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}
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if (outp->info.sorconf.link & 2)
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nvkm_mask(device, 0x612388 + moff, 0x0000001f, link << 4 | sor);
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}
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int
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gm200_sor_route_get(struct nvkm_outp *outp, int *link)
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{
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struct nvkm_device *device = outp->disp->engine.subdev.device;
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const int sublinks = outp->info.sorconf.link;
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int lnk[2], sor[2], m, s;
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for (*link = 0, m = __ffs(outp->info.or) * 2, s = 0; s < 2; m++, s++) {
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if (sublinks & BIT(s)) {
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u32 data = nvkm_rd32(device, 0x612308 + (m * 0x80));
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lnk[s] = (data & 0x00000010) >> 4;
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sor[s] = (data & 0x0000000f);
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if (!sor[s])
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return -1;
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*link |= lnk[s];
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}
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}
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if (sublinks == 3) {
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if (sor[0] != sor[1] || WARN_ON(lnk[0] || !lnk[1]))
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return -1;
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}
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return ((sublinks & 1) ? sor[0] : sor[1]) - 1;
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}
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static const struct nvkm_ior_func
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gm200_sor = {
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.route = {
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.get = gm200_sor_route_get,
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.set = gm200_sor_route_set,
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},
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.state = gf119_sor_state,
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.power = nv50_sor_power,
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.clock = gf119_sor_clock,
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.hdmi = &gm200_sor_hdmi,
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.dp = &gm200_sor_dp,
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.hda = &gf119_sor_hda,
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};
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static int
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gm200_sor_new(struct nvkm_disp *disp, int id)
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{
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struct nvkm_device *device = disp->engine.subdev.device;
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u32 hda;
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if (!((hda = nvkm_rd32(device, 0x08a15c)) & 0x40000000))
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hda = nvkm_rd32(device, 0x101034);
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return nvkm_ior_new_(&gm200_sor, disp, SOR, id, hda & BIT(id));
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}
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static const struct nvkm_disp_func
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gm200_disp = {
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.oneinit = nv50_disp_oneinit,
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.init = gf119_disp_init,
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.fini = gf119_disp_fini,
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.intr = gf119_disp_intr,
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.intr_error = gf119_disp_intr_error,
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.super = gf119_disp_super,
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.uevent = &gf119_disp_chan_uevent,
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.head = { .cnt = gf119_head_cnt, .new = gf119_head_new },
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.dac = { .cnt = gf119_dac_cnt, .new = gf119_dac_new },
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.sor = { .cnt = gf119_sor_cnt, .new = gm200_sor_new },
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.root = { 0,0,GM200_DISP },
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.user = {
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{{0,0,GK104_DISP_CURSOR }, nvkm_disp_chan_new, &gf119_disp_curs },
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{{0,0,GK104_DISP_OVERLAY }, nvkm_disp_chan_new, &gf119_disp_oimm },
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{{0,0,GK110_DISP_BASE_CHANNEL_DMA }, nvkm_disp_chan_new, &gf119_disp_base },
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{{0,0,GM200_DISP_CORE_CHANNEL_DMA }, nvkm_disp_core_new, &gk104_disp_core },
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{{0,0,GK104_DISP_OVERLAY_CONTROL_DMA}, nvkm_disp_chan_new, &gk104_disp_ovly },
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{}
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},
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};
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int
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gm200_disp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
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struct nvkm_disp **pdisp)
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{
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return nvkm_disp_new_(&gm200_disp, device, type, inst, pdisp);
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}
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