152 lines
5.1 KiB
C
152 lines
5.1 KiB
C
/*
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* Copyright 2016 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs <bskeggs@redhat.com>
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*/
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#include "ctxgf100.h"
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#include <subdev/fb.h>
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/*******************************************************************************
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* PGRAPH context implementation
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******************************************************************************/
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void
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gp100_grctx_generate_pagepool(struct gf100_gr_chan *chan, u64 addr)
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{
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gf100_grctx_patch_wr32(chan, 0x40800c, addr >> 8);
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gf100_grctx_patch_wr32(chan, 0x408010, 0x8007d800);
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gf100_grctx_patch_wr32(chan, 0x419004, addr >> 8);
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gf100_grctx_patch_wr32(chan, 0x419008, 0x00000000);
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}
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static void
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gp100_grctx_generate_attrib(struct gf100_gr_chan *chan)
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{
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struct gf100_gr *gr = chan->gr;
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const struct gf100_grctx_func *grctx = gr->func->grctx;
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const u32 alpha = grctx->alpha_nr;
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const u32 attrib = grctx->attrib_nr;
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const int max_batches = 0xffff;
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u32 size = grctx->alpha_nr_max * gr->tpc_total;
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u32 ao = 0;
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u32 bo = ao + size;
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int gpc, ppc, n = 0;
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gf100_grctx_patch_wr32(chan, 0x405830, attrib);
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gf100_grctx_patch_wr32(chan, 0x40585c, alpha);
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gf100_grctx_patch_wr32(chan, 0x4064c4, ((alpha / 4) << 16) | max_batches);
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for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
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for (ppc = 0; ppc < gr->func->ppc_nr; ppc++, n++) {
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const u32 as = alpha * gr->ppc_tpc_nr[gpc][ppc];
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const u32 bs = attrib * gr->ppc_tpc_max;
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const u32 u = 0x418ea0 + (n * 0x04);
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const u32 o = PPC_UNIT(gpc, ppc, 0);
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if (!(gr->ppc_mask[gpc] & (1 << ppc)))
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continue;
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gf100_grctx_patch_wr32(chan, o + 0xc0, bs);
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gf100_grctx_patch_wr32(chan, o + 0xf4, bo);
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gf100_grctx_patch_wr32(chan, o + 0xf0, bs);
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bo += grctx->attrib_nr_max * gr->ppc_tpc_max;
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gf100_grctx_patch_wr32(chan, o + 0xe4, as);
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gf100_grctx_patch_wr32(chan, o + 0xf8, ao);
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ao += grctx->alpha_nr_max * gr->ppc_tpc_nr[gpc][ppc];
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gf100_grctx_patch_wr32(chan, u, bs);
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}
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}
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gf100_grctx_patch_wr32(chan, 0x418eec, 0x00000000);
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gf100_grctx_patch_wr32(chan, 0x41befc, 0x00000000);
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}
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void
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gp100_grctx_generate_attrib_cb(struct gf100_gr_chan *chan, u64 addr, u32 size)
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{
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gm107_grctx_generate_attrib_cb(chan, addr, size);
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gf100_grctx_patch_wr32(chan, 0x419b00, 0x00000000 | addr >> 12);
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gf100_grctx_patch_wr32(chan, 0x419b04, 0x80000000 | size >> 7);
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}
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static u32
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gp100_grctx_generate_attrib_cb_size(struct gf100_gr *gr)
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{
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const struct gf100_grctx_func *grctx = gr->func->grctx;
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u32 size = grctx->alpha_nr_max * gr->tpc_total;
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int gpc;
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for (gpc = 0; gpc < gr->gpc_nr; gpc++)
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size += grctx->attrib_nr_max * gr->func->ppc_nr * gr->ppc_tpc_max;
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return ((size * 0x20) + 128) & ~127;
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}
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void
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gp100_grctx_generate_smid_config(struct gf100_gr *gr)
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{
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struct nvkm_device *device = gr->base.engine.subdev.device;
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const u32 dist_nr = DIV_ROUND_UP(gr->tpc_total, 4);
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u32 dist[TPC_MAX / 4] = {}, gpcs[16] = {};
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u8 sm, i;
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for (sm = 0; sm < gr->sm_nr; sm++) {
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const u8 gpc = gr->sm[sm].gpc;
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const u8 tpc = gr->sm[sm].tpc;
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dist[sm / 4] |= ((gpc << 4) | tpc) << ((sm % 4) * 8);
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gpcs[gpc + (gr->func->gpc_nr * (tpc / 4))] |= sm << ((tpc % 4) * 8);
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}
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for (i = 0; i < dist_nr; i++)
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nvkm_wr32(device, 0x405b60 + (i * 4), dist[i]);
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for (i = 0; i < ARRAY_SIZE(gpcs); i++)
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nvkm_wr32(device, 0x405ba0 + (i * 4), gpcs[i]);
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}
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const struct gf100_grctx_func
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gp100_grctx = {
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.main = gf100_grctx_generate_main,
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.unkn = gk104_grctx_generate_unkn,
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.bundle = gm107_grctx_generate_bundle,
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.bundle_size = 0x3000,
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.bundle_min_gpm_fifo_depth = 0x180,
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.bundle_token_limit = 0x1080,
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.pagepool = gp100_grctx_generate_pagepool,
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.pagepool_size = 0x20000,
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.attrib_cb_size = gp100_grctx_generate_attrib_cb_size,
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.attrib_cb = gp100_grctx_generate_attrib_cb,
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.attrib = gp100_grctx_generate_attrib,
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.attrib_nr_max = 0x660,
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.attrib_nr = 0x440,
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.alpha_nr_max = 0xc00,
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.alpha_nr = 0x800,
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.sm_id = gm107_grctx_generate_sm_id,
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.rop_mapping = gf117_grctx_generate_rop_mapping,
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.dist_skip_table = gm200_grctx_generate_dist_skip_table,
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.r406500 = gm200_grctx_generate_r406500,
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.gpc_tpc_nr = gk104_grctx_generate_gpc_tpc_nr,
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.tpc_mask = gm200_grctx_generate_tpc_mask,
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.smid_config = gp100_grctx_generate_smid_config,
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.r419a3c = gm200_grctx_generate_r419a3c,
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};
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