348 lines
10 KiB
C
348 lines
10 KiB
C
/*
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* Copyright 2019 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "gf100.h"
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#include "ctxgf100.h"
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#include <core/firmware.h>
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#include <subdev/acr.h>
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#include <subdev/timer.h>
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#include <subdev/vfn.h>
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#include <nvfw/flcn.h>
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#include <nvif/class.h>
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static void
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ga102_gr_zbc_clear_color(struct gf100_gr *gr, int zbc)
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{
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struct nvkm_device *device = gr->base.engine.subdev.device;
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u32 invalid[] = { 0, 0, 0, 0 }, *color;
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if (gr->zbc_color[zbc].format)
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color = gr->zbc_color[zbc].l2;
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else
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color = invalid;
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nvkm_mask(device, 0x41bcb4, 0x0000001f, zbc);
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nvkm_wr32(device, 0x41bcec, color[0]);
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nvkm_wr32(device, 0x41bcf0, color[1]);
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nvkm_wr32(device, 0x41bcf4, color[2]);
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nvkm_wr32(device, 0x41bcf8, color[3]);
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}
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static const struct gf100_gr_func_zbc
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ga102_gr_zbc = {
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.clear_color = ga102_gr_zbc_clear_color,
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.clear_depth = gp100_gr_zbc_clear_depth,
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.stencil_get = gp102_gr_zbc_stencil_get,
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.clear_stencil = gp102_gr_zbc_clear_stencil,
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};
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static void
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ga102_gr_gpccs_reset(struct gf100_gr *gr)
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{
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struct nvkm_device *device = gr->base.engine.subdev.device;
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nvkm_wr32(device, 0x41a610, 0x00000000);
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nvkm_msec(device, 1, NVKM_DELAY);
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nvkm_wr32(device, 0x41a610, 0x00000001);
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}
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static const struct nvkm_acr_lsf_func
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ga102_gr_gpccs_acr = {
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.flags = NVKM_ACR_LSF_FORCE_PRIV_LOAD,
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.bl_entry = 0x3400,
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.bld_size = sizeof(struct flcn_bl_dmem_desc_v2),
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.bld_write = gp108_gr_acr_bld_write,
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.bld_patch = gp108_gr_acr_bld_patch,
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};
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static void
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ga102_gr_fecs_reset(struct gf100_gr *gr)
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{
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struct nvkm_device *device = gr->base.engine.subdev.device;
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nvkm_wr32(device, 0x409614, 0x00000010);
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nvkm_wr32(device, 0x41a614, 0x00000020);
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nvkm_usec(device, 10, NVKM_DELAY);
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nvkm_wr32(device, 0x409614, 0x00000110);
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nvkm_wr32(device, 0x41a614, 0x00000a20);
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nvkm_usec(device, 10, NVKM_DELAY);
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nvkm_rd32(device, 0x409614);
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nvkm_rd32(device, 0x41a614);
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}
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static const struct nvkm_acr_lsf_func
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ga102_gr_fecs_acr = {
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.bl_entry = 0x7e00,
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.bld_size = sizeof(struct flcn_bl_dmem_desc_v2),
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.bld_write = gp108_gr_acr_bld_write,
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.bld_patch = gp108_gr_acr_bld_patch,
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};
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static void
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ga102_gr_init_rop_exceptions(struct gf100_gr *gr)
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{
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struct nvkm_device *device = gr->base.engine.subdev.device;
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nvkm_wr32(device, 0x41bcbc, 0x40000000);
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nvkm_wr32(device, 0x41bc38, 0x40000000);
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nvkm_wr32(device, 0x41ac94, nvkm_rd32(device, 0x502c94));
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}
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static void
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ga102_gr_init_40a790(struct gf100_gr *gr)
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{
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nvkm_wr32(gr->base.engine.subdev.device, 0x40a790, 0xc0000000);
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}
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static void
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ga102_gr_init_gpc_mmu(struct gf100_gr *gr)
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{
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struct nvkm_device *device = gr->base.engine.subdev.device;
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nvkm_wr32(device, 0x418880, nvkm_rd32(device, 0x100c80) & 0xf8001fff);
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nvkm_wr32(device, 0x418894, 0x00000000);
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nvkm_wr32(device, 0x4188b4, nvkm_rd32(device, 0x100cc8));
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nvkm_wr32(device, 0x4188b8, nvkm_rd32(device, 0x100ccc));
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nvkm_wr32(device, 0x4188b0, nvkm_rd32(device, 0x100cc4));
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}
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static struct nvkm_intr *
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ga102_gr_oneinit_intr(struct gf100_gr *gr, enum nvkm_intr_type *pvector)
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{
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struct nvkm_device *device = gr->base.engine.subdev.device;
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*pvector = nvkm_rd32(device, 0x400154) & 0x00000fff;
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return &device->vfn->intr;
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}
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static const struct gf100_gr_func
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ga102_gr = {
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.oneinit_intr = ga102_gr_oneinit_intr,
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.oneinit_tiles = gm200_gr_oneinit_tiles,
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.oneinit_sm_id = gv100_gr_oneinit_sm_id,
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.init = gf100_gr_init,
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.init_419bd8 = gv100_gr_init_419bd8,
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.init_gpc_mmu = ga102_gr_init_gpc_mmu,
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.init_vsc_stream_master = gk104_gr_init_vsc_stream_master,
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.init_zcull = tu102_gr_init_zcull,
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.init_num_active_ltcs = gf100_gr_init_num_active_ltcs,
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.init_swdx_pes_mask = gp102_gr_init_swdx_pes_mask,
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.init_fs = tu102_gr_init_fs,
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.init_fecs_exceptions = tu102_gr_init_fecs_exceptions,
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.init_40a790 = ga102_gr_init_40a790,
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.init_ds_hww_esr_2 = gm200_gr_init_ds_hww_esr_2,
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.init_sked_hww_esr = gk104_gr_init_sked_hww_esr,
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.init_ppc_exceptions = gk104_gr_init_ppc_exceptions,
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.init_504430 = gv100_gr_init_504430,
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.init_shader_exceptions = gv100_gr_init_shader_exceptions,
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.init_rop_exceptions = ga102_gr_init_rop_exceptions,
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.init_4188a4 = gv100_gr_init_4188a4,
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.trap_mp = gv100_gr_trap_mp,
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.fecs.reset = ga102_gr_fecs_reset,
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.gpccs.reset = ga102_gr_gpccs_reset,
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.rops = gm200_gr_rops,
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.gpc_nr = 7,
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.tpc_nr = 6,
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.ppc_nr = 3,
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.grctx = &ga102_grctx,
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.zbc = &ga102_gr_zbc,
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.sclass = {
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{ -1, -1, FERMI_TWOD_A },
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{ -1, -1, KEPLER_INLINE_TO_MEMORY_B },
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{ -1, -1, AMPERE_B, &gf100_fermi },
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{ -1, -1, AMPERE_COMPUTE_B },
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{}
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}
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};
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MODULE_FIRMWARE("nvidia/ga102/gr/fecs_bl.bin");
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MODULE_FIRMWARE("nvidia/ga102/gr/fecs_sig.bin");
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MODULE_FIRMWARE("nvidia/ga102/gr/gpccs_bl.bin");
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MODULE_FIRMWARE("nvidia/ga102/gr/gpccs_sig.bin");
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MODULE_FIRMWARE("nvidia/ga102/gr/NET_img.bin");
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MODULE_FIRMWARE("nvidia/ga103/gr/fecs_bl.bin");
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MODULE_FIRMWARE("nvidia/ga103/gr/fecs_sig.bin");
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MODULE_FIRMWARE("nvidia/ga103/gr/gpccs_bl.bin");
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MODULE_FIRMWARE("nvidia/ga103/gr/gpccs_sig.bin");
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MODULE_FIRMWARE("nvidia/ga103/gr/NET_img.bin");
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MODULE_FIRMWARE("nvidia/ga104/gr/fecs_bl.bin");
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MODULE_FIRMWARE("nvidia/ga104/gr/fecs_sig.bin");
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MODULE_FIRMWARE("nvidia/ga104/gr/gpccs_bl.bin");
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MODULE_FIRMWARE("nvidia/ga104/gr/gpccs_sig.bin");
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MODULE_FIRMWARE("nvidia/ga104/gr/NET_img.bin");
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MODULE_FIRMWARE("nvidia/ga106/gr/fecs_bl.bin");
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MODULE_FIRMWARE("nvidia/ga106/gr/fecs_sig.bin");
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MODULE_FIRMWARE("nvidia/ga106/gr/gpccs_bl.bin");
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MODULE_FIRMWARE("nvidia/ga106/gr/gpccs_sig.bin");
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MODULE_FIRMWARE("nvidia/ga106/gr/NET_img.bin");
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MODULE_FIRMWARE("nvidia/ga107/gr/fecs_bl.bin");
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MODULE_FIRMWARE("nvidia/ga107/gr/fecs_sig.bin");
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MODULE_FIRMWARE("nvidia/ga107/gr/gpccs_bl.bin");
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MODULE_FIRMWARE("nvidia/ga107/gr/gpccs_sig.bin");
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MODULE_FIRMWARE("nvidia/ga107/gr/NET_img.bin");
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struct netlist_region {
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u32 region_id;
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u32 data_size;
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u32 data_offset;
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};
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struct netlist_image_header {
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u32 version;
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u32 regions;
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};
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struct netlist_image {
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struct netlist_image_header header;
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struct netlist_region regions[];
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};
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struct netlist_av64 {
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u32 addr;
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u32 data_hi;
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u32 data_lo;
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};
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static int
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ga102_gr_av64_to_init(struct nvkm_blob *blob, struct gf100_gr_pack **ppack)
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{
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struct gf100_gr_init *init;
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struct gf100_gr_pack *pack;
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int nent;
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int i;
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nent = (blob->size / sizeof(struct netlist_av64));
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pack = vzalloc((sizeof(*pack) * 2) + (sizeof(*init) * (nent + 1)));
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if (!pack)
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return -ENOMEM;
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init = (void *)(pack + 2);
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pack[0].init = init;
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pack[0].type = 64;
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for (i = 0; i < nent; i++) {
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struct gf100_gr_init *ent = &init[i];
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struct netlist_av64 *av = &((struct netlist_av64 *)blob->data)[i];
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ent->addr = av->addr;
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ent->data = ((u64)av->data_hi << 32) | av->data_lo;
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ent->count = 1;
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ent->pitch = 1;
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}
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*ppack = pack;
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return 0;
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}
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static int
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ga102_gr_load(struct gf100_gr *gr, int ver, const struct gf100_gr_fwif *fwif)
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{
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struct nvkm_subdev *subdev = &gr->base.engine.subdev;
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const struct firmware *fw;
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const struct netlist_image *net;
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const struct netlist_region *fecs_inst = NULL;
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const struct netlist_region *fecs_data = NULL;
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const struct netlist_region *gpccs_inst = NULL;
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const struct netlist_region *gpccs_data = NULL;
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int ret, i;
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ret = nvkm_firmware_get(subdev, "gr/NET_img", 0, &fw);
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if (ret)
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return ret;
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net = (const void *)fw->data;
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nvkm_debug(subdev, "netlist version %d, %d regions\n",
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net->header.version, net->header.regions);
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for (i = 0; i < net->header.regions; i++) {
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const struct netlist_region *reg = &net->regions[i];
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struct nvkm_blob blob = {
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.data = (void *)fw->data + reg->data_offset,
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.size = reg->data_size,
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};
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nvkm_debug(subdev, "\t%2d: %08x %08x\n",
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reg->region_id, reg->data_offset, reg->data_size);
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switch (reg->region_id) {
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case 0: fecs_data = reg; break;
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case 1: fecs_inst = reg; break;
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case 2: gpccs_data = reg; break;
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case 3: gpccs_inst = reg; break;
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case 4: gk20a_gr_av_to_init(&blob, &gr->bundle); break;
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case 5: gk20a_gr_aiv_to_init(&blob, &gr->sw_ctx); break;
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case 7: gk20a_gr_av_to_method(&blob, &gr->method); break;
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case 28: tu102_gr_av_to_init_veid(&blob, &gr->bundle_veid); break;
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case 34: ga102_gr_av64_to_init(&blob, &gr->bundle64); break;
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case 48: gk20a_gr_av_to_init(&blob, &gr->sw_nonctx1); break;
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case 49: gk20a_gr_av_to_init(&blob, &gr->sw_nonctx2); break;
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case 50: gk20a_gr_av_to_init(&blob, &gr->sw_nonctx3); break;
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case 51: gk20a_gr_av_to_init(&blob, &gr->sw_nonctx4); break;
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default:
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break;
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}
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}
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ret = nvkm_acr_lsfw_load_bl_sig_net(subdev, &gr->fecs.falcon, NVKM_ACR_LSF_FECS,
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"gr/fecs_", ver, fwif->fecs,
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fw->data + fecs_inst->data_offset,
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fecs_inst->data_size,
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fw->data + fecs_data->data_offset,
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fecs_data->data_size);
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if (ret)
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return ret;
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ret = nvkm_acr_lsfw_load_bl_sig_net(subdev, &gr->gpccs.falcon, NVKM_ACR_LSF_GPCCS,
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"gr/gpccs_", ver, fwif->gpccs,
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fw->data + gpccs_inst->data_offset,
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gpccs_inst->data_size,
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fw->data + gpccs_data->data_offset,
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gpccs_data->data_size);
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if (ret)
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return ret;
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gr->firmware = true;
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nvkm_firmware_put(fw);
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return 0;
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}
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static const struct gf100_gr_fwif
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ga102_gr_fwif[] = {
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{ 0, ga102_gr_load, &ga102_gr, &ga102_gr_fecs_acr, &ga102_gr_gpccs_acr },
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{ -1, gm200_gr_nofw },
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{}
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};
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int
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ga102_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
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{
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return gf100_gr_new_(ga102_gr_fwif, device, type, inst, pgr);
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}
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