297 lines
9.4 KiB
C
297 lines
9.4 KiB
C
/*
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* Copyright 2015 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs <bskeggs@redhat.com>
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*/
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#include "gf100.h"
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#include "ctxgf100.h"
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#include <core/firmware.h>
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#include <subdev/acr.h>
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#include <nvfw/flcn.h>
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#include <nvif/class.h>
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int
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gm200_gr_nofw(struct gf100_gr *gr, int ver, const struct gf100_gr_fwif *fwif)
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{
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nvkm_warn(&gr->base.engine.subdev, "firmware unavailable\n");
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return -ENODEV;
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}
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/*******************************************************************************
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* PGRAPH engine/subdev functions
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******************************************************************************/
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static void
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gm200_gr_acr_bld_patch(struct nvkm_acr *acr, u32 bld, s64 adjust)
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{
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struct flcn_bl_dmem_desc_v1 hdr;
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nvkm_robj(acr->wpr, bld, &hdr, sizeof(hdr));
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hdr.code_dma_base = hdr.code_dma_base + adjust;
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hdr.data_dma_base = hdr.data_dma_base + adjust;
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nvkm_wobj(acr->wpr, bld, &hdr, sizeof(hdr));
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flcn_bl_dmem_desc_v1_dump(&acr->subdev, &hdr);
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}
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static void
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gm200_gr_acr_bld_write(struct nvkm_acr *acr, u32 bld,
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struct nvkm_acr_lsfw *lsfw)
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{
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const u64 base = lsfw->offset.img + lsfw->app_start_offset;
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const u64 code = base + lsfw->app_resident_code_offset;
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const u64 data = base + lsfw->app_resident_data_offset;
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const struct flcn_bl_dmem_desc_v1 hdr = {
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.ctx_dma = FALCON_DMAIDX_UCODE,
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.code_dma_base = code,
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.non_sec_code_off = lsfw->app_resident_code_offset,
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.non_sec_code_size = lsfw->app_resident_code_size,
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.code_entry_point = lsfw->app_imem_entry,
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.data_dma_base = data,
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.data_size = lsfw->app_resident_data_size,
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};
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nvkm_wobj(acr->wpr, bld, &hdr, sizeof(hdr));
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}
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const struct nvkm_acr_lsf_func
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gm200_gr_gpccs_acr = {
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.flags = NVKM_ACR_LSF_FORCE_PRIV_LOAD,
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.bld_size = sizeof(struct flcn_bl_dmem_desc_v1),
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.bld_write = gm200_gr_acr_bld_write,
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.bld_patch = gm200_gr_acr_bld_patch,
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};
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const struct nvkm_acr_lsf_func
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gm200_gr_fecs_acr = {
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.bld_size = sizeof(struct flcn_bl_dmem_desc_v1),
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.bld_write = gm200_gr_acr_bld_write,
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.bld_patch = gm200_gr_acr_bld_patch,
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};
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int
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gm200_gr_rops(struct gf100_gr *gr)
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{
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return nvkm_rd32(gr->base.engine.subdev.device, 0x12006c);
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}
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void
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gm200_gr_init_ds_hww_esr_2(struct gf100_gr *gr)
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{
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struct nvkm_device *device = gr->base.engine.subdev.device;
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nvkm_wr32(device, 0x405848, 0xc0000000);
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nvkm_mask(device, 0x40584c, 0x00000001, 0x00000001);
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}
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void
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gm200_gr_init_num_active_ltcs(struct gf100_gr *gr)
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{
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struct nvkm_device *device = gr->base.engine.subdev.device;
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nvkm_wr32(device, GPC_BCAST(0x08ac), nvkm_rd32(device, 0x100800));
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nvkm_wr32(device, GPC_BCAST(0x033c), nvkm_rd32(device, 0x100804));
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}
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void
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gm200_gr_init_gpc_mmu(struct gf100_gr *gr)
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{
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struct nvkm_device *device = gr->base.engine.subdev.device;
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nvkm_wr32(device, 0x418880, nvkm_rd32(device, 0x100c80) & 0xf0001fff);
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nvkm_wr32(device, 0x418890, 0x00000000);
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nvkm_wr32(device, 0x418894, 0x00000000);
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nvkm_wr32(device, 0x4188b4, nvkm_rd32(device, 0x100cc8));
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nvkm_wr32(device, 0x4188b8, nvkm_rd32(device, 0x100ccc));
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nvkm_wr32(device, 0x4188b0, nvkm_rd32(device, 0x100cc4));
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}
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static void
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gm200_gr_init_rop_active_fbps(struct gf100_gr *gr)
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{
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struct nvkm_device *device = gr->base.engine.subdev.device;
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const u32 fbp_count = nvkm_rd32(device, 0x12006c);
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nvkm_mask(device, 0x408850, 0x0000000f, fbp_count); /* zrop */
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nvkm_mask(device, 0x408958, 0x0000000f, fbp_count); /* crop */
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}
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static u8
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gm200_gr_tile_map_6_24[] = {
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0, 1, 2, 3, 4, 5, 3, 4, 5, 0, 1, 2, 0, 1, 2, 3, 4, 5, 3, 4, 5, 0, 1, 2,
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};
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static u8
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gm200_gr_tile_map_4_16[] = {
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0, 1, 2, 3, 2, 3, 0, 1, 3, 0, 1, 2, 1, 2, 3, 0,
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};
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static u8
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gm200_gr_tile_map_2_8[] = {
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0, 1, 1, 0, 0, 1, 1, 0,
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};
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int
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gm200_gr_oneinit_sm_id(struct gf100_gr *gr)
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{
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/*XXX: There's a different algorithm here I've not yet figured out. */
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return gf100_gr_oneinit_sm_id(gr);
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}
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void
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gm200_gr_oneinit_tiles(struct gf100_gr *gr)
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{
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/*XXX: Not sure what this is about. The algorithm from NVGPU
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* seems to work for all boards I tried from earlier (and
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* later) GPUs except in these specific configurations.
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*
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* Let's just hardcode them for now.
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*/
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if (gr->gpc_nr == 2 && gr->tpc_total == 8) {
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memcpy(gr->tile, gm200_gr_tile_map_2_8, gr->tpc_total);
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gr->screen_tile_row_offset = 1;
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} else
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if (gr->gpc_nr == 4 && gr->tpc_total == 16) {
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memcpy(gr->tile, gm200_gr_tile_map_4_16, gr->tpc_total);
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gr->screen_tile_row_offset = 4;
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} else
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if (gr->gpc_nr == 6 && gr->tpc_total == 24) {
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memcpy(gr->tile, gm200_gr_tile_map_6_24, gr->tpc_total);
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gr->screen_tile_row_offset = 5;
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} else {
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gf100_gr_oneinit_tiles(gr);
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}
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}
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static const struct gf100_gr_func
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gm200_gr = {
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.oneinit_tiles = gm200_gr_oneinit_tiles,
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.oneinit_sm_id = gm200_gr_oneinit_sm_id,
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.init = gf100_gr_init,
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.init_gpc_mmu = gm200_gr_init_gpc_mmu,
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.init_bios = gm107_gr_init_bios,
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.init_vsc_stream_master = gk104_gr_init_vsc_stream_master,
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.init_zcull = gf117_gr_init_zcull,
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.init_num_active_ltcs = gm200_gr_init_num_active_ltcs,
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.init_rop_active_fbps = gm200_gr_init_rop_active_fbps,
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.init_fecs_exceptions = gf100_gr_init_fecs_exceptions,
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.init_ds_hww_esr_2 = gm200_gr_init_ds_hww_esr_2,
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.init_sked_hww_esr = gk104_gr_init_sked_hww_esr,
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.init_419cc0 = gf100_gr_init_419cc0,
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.init_ppc_exceptions = gk104_gr_init_ppc_exceptions,
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.init_tex_hww_esr = gf100_gr_init_tex_hww_esr,
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.init_504430 = gm107_gr_init_504430,
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.init_shader_exceptions = gm107_gr_init_shader_exceptions,
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.init_rop_exceptions = gf100_gr_init_rop_exceptions,
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.init_exception2 = gf100_gr_init_exception2,
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.init_400054 = gm107_gr_init_400054,
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.trap_mp = gf100_gr_trap_mp,
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.fecs.reset = gf100_gr_fecs_reset,
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.rops = gm200_gr_rops,
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.tpc_nr = 4,
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.ppc_nr = 2,
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.grctx = &gm200_grctx,
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.zbc = &gf100_gr_zbc,
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.sclass = {
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{ -1, -1, FERMI_TWOD_A },
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{ -1, -1, KEPLER_INLINE_TO_MEMORY_B },
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{ -1, -1, MAXWELL_B, &gf100_fermi },
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{ -1, -1, MAXWELL_COMPUTE_B },
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{}
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}
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};
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int
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gm200_gr_load(struct gf100_gr *gr, int ver, const struct gf100_gr_fwif *fwif)
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{
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int ret;
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ret = nvkm_acr_lsfw_load_bl_inst_data_sig(&gr->base.engine.subdev,
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&gr->fecs.falcon,
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NVKM_ACR_LSF_FECS,
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"gr/fecs_", ver, fwif->fecs);
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if (ret)
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return ret;
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ret = nvkm_acr_lsfw_load_bl_inst_data_sig(&gr->base.engine.subdev,
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&gr->gpccs.falcon,
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NVKM_ACR_LSF_GPCCS,
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"gr/gpccs_", ver,
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fwif->gpccs);
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if (ret)
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return ret;
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gr->firmware = true;
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return gk20a_gr_load_sw(gr, "gr/", ver);
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}
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MODULE_FIRMWARE("nvidia/gm200/gr/fecs_bl.bin");
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MODULE_FIRMWARE("nvidia/gm200/gr/fecs_inst.bin");
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MODULE_FIRMWARE("nvidia/gm200/gr/fecs_data.bin");
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MODULE_FIRMWARE("nvidia/gm200/gr/fecs_sig.bin");
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MODULE_FIRMWARE("nvidia/gm200/gr/gpccs_bl.bin");
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MODULE_FIRMWARE("nvidia/gm200/gr/gpccs_inst.bin");
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MODULE_FIRMWARE("nvidia/gm200/gr/gpccs_data.bin");
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MODULE_FIRMWARE("nvidia/gm200/gr/gpccs_sig.bin");
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MODULE_FIRMWARE("nvidia/gm200/gr/sw_ctx.bin");
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MODULE_FIRMWARE("nvidia/gm200/gr/sw_nonctx.bin");
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MODULE_FIRMWARE("nvidia/gm200/gr/sw_bundle_init.bin");
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MODULE_FIRMWARE("nvidia/gm200/gr/sw_method_init.bin");
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MODULE_FIRMWARE("nvidia/gm204/gr/fecs_bl.bin");
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MODULE_FIRMWARE("nvidia/gm204/gr/fecs_inst.bin");
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MODULE_FIRMWARE("nvidia/gm204/gr/fecs_data.bin");
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MODULE_FIRMWARE("nvidia/gm204/gr/fecs_sig.bin");
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MODULE_FIRMWARE("nvidia/gm204/gr/gpccs_bl.bin");
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MODULE_FIRMWARE("nvidia/gm204/gr/gpccs_inst.bin");
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MODULE_FIRMWARE("nvidia/gm204/gr/gpccs_data.bin");
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MODULE_FIRMWARE("nvidia/gm204/gr/gpccs_sig.bin");
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MODULE_FIRMWARE("nvidia/gm204/gr/sw_ctx.bin");
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MODULE_FIRMWARE("nvidia/gm204/gr/sw_nonctx.bin");
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MODULE_FIRMWARE("nvidia/gm204/gr/sw_bundle_init.bin");
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MODULE_FIRMWARE("nvidia/gm204/gr/sw_method_init.bin");
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MODULE_FIRMWARE("nvidia/gm206/gr/fecs_bl.bin");
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MODULE_FIRMWARE("nvidia/gm206/gr/fecs_inst.bin");
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MODULE_FIRMWARE("nvidia/gm206/gr/fecs_data.bin");
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MODULE_FIRMWARE("nvidia/gm206/gr/fecs_sig.bin");
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MODULE_FIRMWARE("nvidia/gm206/gr/gpccs_bl.bin");
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MODULE_FIRMWARE("nvidia/gm206/gr/gpccs_inst.bin");
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MODULE_FIRMWARE("nvidia/gm206/gr/gpccs_data.bin");
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MODULE_FIRMWARE("nvidia/gm206/gr/gpccs_sig.bin");
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MODULE_FIRMWARE("nvidia/gm206/gr/sw_ctx.bin");
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MODULE_FIRMWARE("nvidia/gm206/gr/sw_nonctx.bin");
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MODULE_FIRMWARE("nvidia/gm206/gr/sw_bundle_init.bin");
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MODULE_FIRMWARE("nvidia/gm206/gr/sw_method_init.bin");
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static const struct gf100_gr_fwif
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gm200_gr_fwif[] = {
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{ 0, gm200_gr_load, &gm200_gr, &gm200_gr_fecs_acr, &gm200_gr_gpccs_acr },
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{ -1, gm200_gr_nofw },
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{}
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};
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int
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gm200_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
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{
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return gf100_gr_new_(gm200_gr_fwif, device, type, inst, pgr);
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}
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