174 lines
5.5 KiB
C
174 lines
5.5 KiB
C
/*
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* Copyright 2013 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include <subdev/bios.h>
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#include <subdev/bios/bit.h>
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#include <subdev/bios/timing.h>
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u32
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nvbios_timingTe(struct nvkm_bios *bios,
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u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *snr, u8 *ssz)
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{
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struct bit_entry bit_P;
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u32 timing = 0;
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if (!bit_entry(bios, 'P', &bit_P)) {
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if (bit_P.version == 1)
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timing = nvbios_rd32(bios, bit_P.offset + 4);
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else
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if (bit_P.version == 2)
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timing = nvbios_rd32(bios, bit_P.offset + 8);
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if (timing) {
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*ver = nvbios_rd08(bios, timing + 0);
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switch (*ver) {
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case 0x10:
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*hdr = nvbios_rd08(bios, timing + 1);
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*cnt = nvbios_rd08(bios, timing + 2);
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*len = nvbios_rd08(bios, timing + 3);
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*snr = 0;
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*ssz = 0;
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return timing;
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case 0x20:
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*hdr = nvbios_rd08(bios, timing + 1);
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*cnt = nvbios_rd08(bios, timing + 5);
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*len = nvbios_rd08(bios, timing + 2);
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*snr = nvbios_rd08(bios, timing + 4);
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*ssz = nvbios_rd08(bios, timing + 3);
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return timing;
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default:
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break;
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}
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}
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}
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return 0;
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}
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u32
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nvbios_timingEe(struct nvkm_bios *bios, int idx,
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u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
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{
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u8 snr, ssz;
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u32 timing = nvbios_timingTe(bios, ver, hdr, cnt, len, &snr, &ssz);
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if (timing && idx < *cnt) {
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timing += *hdr + idx * (*len + (snr * ssz));
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*hdr = *len;
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*cnt = snr;
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*len = ssz;
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return timing;
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}
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return 0;
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}
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u32
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nvbios_timingEp(struct nvkm_bios *bios, int idx,
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u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_ramcfg *p)
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{
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u32 data = nvbios_timingEe(bios, idx, ver, hdr, cnt, len), temp;
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p->timing_ver = *ver;
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p->timing_hdr = *hdr;
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switch (!!data * *ver) {
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case 0x10:
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p->timing_10_WR = nvbios_rd08(bios, data + 0x00);
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p->timing_10_WTR = nvbios_rd08(bios, data + 0x01);
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p->timing_10_CL = nvbios_rd08(bios, data + 0x02);
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p->timing_10_RC = nvbios_rd08(bios, data + 0x03);
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p->timing_10_RFC = nvbios_rd08(bios, data + 0x05);
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p->timing_10_RAS = nvbios_rd08(bios, data + 0x07);
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p->timing_10_RP = nvbios_rd08(bios, data + 0x09);
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p->timing_10_RCDRD = nvbios_rd08(bios, data + 0x0a);
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p->timing_10_RCDWR = nvbios_rd08(bios, data + 0x0b);
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p->timing_10_RRD = nvbios_rd08(bios, data + 0x0c);
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p->timing_10_13 = nvbios_rd08(bios, data + 0x0d);
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p->timing_10_ODT = nvbios_rd08(bios, data + 0x0e) & 0x07;
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if (p->ramcfg_ver >= 0x10)
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p->ramcfg_RON = nvbios_rd08(bios, data + 0x0e) & 0x07;
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p->timing_10_24 = 0xff;
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p->timing_10_21 = 0;
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p->timing_10_20 = 0;
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p->timing_10_CWL = 0;
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p->timing_10_18 = 0;
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p->timing_10_16 = 0;
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switch (min_t(u8, *hdr, 25)) {
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case 25:
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p->timing_10_24 = nvbios_rd08(bios, data + 0x18);
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fallthrough;
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case 24:
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case 23:
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case 22:
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p->timing_10_21 = nvbios_rd08(bios, data + 0x15);
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fallthrough;
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case 21:
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p->timing_10_20 = nvbios_rd08(bios, data + 0x14);
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fallthrough;
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case 20:
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p->timing_10_CWL = nvbios_rd08(bios, data + 0x13);
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fallthrough;
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case 19:
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p->timing_10_18 = nvbios_rd08(bios, data + 0x12);
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fallthrough;
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case 18:
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case 17:
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p->timing_10_16 = nvbios_rd08(bios, data + 0x10);
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}
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break;
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case 0x20:
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p->timing[0] = nvbios_rd32(bios, data + 0x00);
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p->timing[1] = nvbios_rd32(bios, data + 0x04);
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p->timing[2] = nvbios_rd32(bios, data + 0x08);
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p->timing[3] = nvbios_rd32(bios, data + 0x0c);
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p->timing[4] = nvbios_rd32(bios, data + 0x10);
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p->timing[5] = nvbios_rd32(bios, data + 0x14);
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p->timing[6] = nvbios_rd32(bios, data + 0x18);
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p->timing[7] = nvbios_rd32(bios, data + 0x1c);
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p->timing[8] = nvbios_rd32(bios, data + 0x20);
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p->timing[9] = nvbios_rd32(bios, data + 0x24);
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p->timing[10] = nvbios_rd32(bios, data + 0x28);
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p->timing_20_2e_03 = (nvbios_rd08(bios, data + 0x2e) & 0x03) >> 0;
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p->timing_20_2e_30 = (nvbios_rd08(bios, data + 0x2e) & 0x30) >> 4;
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p->timing_20_2e_c0 = (nvbios_rd08(bios, data + 0x2e) & 0xc0) >> 6;
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p->timing_20_2f_03 = (nvbios_rd08(bios, data + 0x2f) & 0x03) >> 0;
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temp = nvbios_rd16(bios, data + 0x2c);
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p->timing_20_2c_003f = (temp & 0x003f) >> 0;
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p->timing_20_2c_1fc0 = (temp & 0x1fc0) >> 6;
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p->timing_20_30_07 = (nvbios_rd08(bios, data + 0x30) & 0x07) >> 0;
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p->timing_20_30_f8 = (nvbios_rd08(bios, data + 0x30) & 0xf8) >> 3;
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temp = nvbios_rd16(bios, data + 0x31);
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p->timing_20_31_0007 = (temp & 0x0007) >> 0;
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p->timing_20_31_0078 = (temp & 0x0078) >> 3;
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p->timing_20_31_0780 = (temp & 0x0780) >> 7;
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p->timing_20_31_0800 = (temp & 0x0800) >> 11;
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p->timing_20_31_7000 = (temp & 0x7000) >> 12;
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p->timing_20_31_8000 = (temp & 0x8000) >> 15;
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break;
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default:
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data = 0;
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break;
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}
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return data;
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}
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